void up_dumpnvic(FAR const char *msg) { #ifdef CONFIG_DEBUG_INFO irqstate_t flags; int i; /* The following requires exclusive access to the NVIC/SYSCON registers */ flags = enter_critical_section(); _info("NVIC: %s\n", msg); _info(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n", getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER), getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); for (i = 0 ; i < 8; i += 4) { _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n", i, getreg32(ARMV6M_NVIC_IPR(i)), i+1, getreg32(ARMV6M_NVIC_IPR(i+1)), i+2, getreg32(ARMV6M_NVIC_IPR(i+2)), i+3, getreg32(ARMV6M_NVIC_IPR(i+3))); } _info("SYSCON:\n"); _info(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n", getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR)); _info(" CCR: %08x SHPR2: %08x SHPR3: %08x\n", getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); leave_critical_section(flags); #endif }
void up_irqinitialize(void) { uint32_t regaddr; int i; /* Disable all interrupts */ putreg32(0xffffffff, ARMV6M_NVIC_ICER); /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); /* Now set all of the interrupt lines to the default priority */ for (i = 0; i < 8; i++) { regaddr = ARMV6M_NVIC_IPR(i); putreg32(DEFPRIORITY32, regaddr); } /* currents_regs is non-NULL only while processing an interrupt */ current_regs = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(KL_IRQ_SVCALL, up_svcall); irq_attach(KL_IRQ_HARDFAULT, up_hardfault); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG irq_attach(KL_IRQ_NMI, kl_nmi); irq_attach(KL_IRQ_PENDSV, kl_pendsv); irq_attach(KL_IRQ_RESERVED, kl_reserved); #endif kl_dumpnvic("initial", NR_IRQS); /* Initialize logic to support a second level of interrupt decoding for * configured pin interrupts. */ #ifdef CONFIG_GPIO_IRQ kl_gpioirqinitialize(); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ irqenable(); #endif }