/* * Entry point for upper layers to restart current cal. * Reset the calibration valid bit in channel. */ HAL_BOOL ar5416ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) { struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); HAL_CAL_LIST *currCal = cal->cal_curr; if (!AR_SREV_SOWL_10_OR_LATER(ah)) return AH_FALSE; if (currCal == AH_NULL) return AH_FALSE; if (ichan == AH_NULL) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u/0x%x; no mapping\n", __func__, chan->ic_freq, chan->ic_flags); return AH_FALSE; } /* * Expected that this calibration has run before, post-reset. * Current state should be done */ if (currCal->calState != CAL_DONE) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Calibration state incorrect, %d\n", __func__, currCal->calState); return AH_FALSE; } /* Verify Cal is supported on this channel */ if (!ar5416IsCalSupp(ah, chan, currCal->calData->calType)) return AH_FALSE; HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: Resetting Cal %d state for channel %u/0x%x\n", __func__, currCal->calData->calType, chan->ic_freq, chan->ic_flags); /* Disable cal validity in channel */ ichan->calValid &= ~currCal->calData->calType; currCal->calState = CAL_WAITING; return AH_TRUE; }
static HAL_BOOL ar2133SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) { u_int32_t channelSel = 0; u_int32_t bModeSynth = 0; u_int32_t aModeRefSel = 0; u_int32_t reg32 = 0; u_int16_t freq; CHAN_CENTERS centers; OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel); ar5416GetChannelCenters(ah, chan, ¢ers); freq = centers.synth_center; if (freq < 4800) { u_int32_t txctl; if (((freq - 2192) % 5) == 0) { channelSel = ((freq - 672) * 2 - 3040)/10; bModeSynth = 0; } else if (((freq - 2224) % 5) == 0) { channelSel = ((freq - 704) * 2 - 3040) / 10; bModeSynth = 1; } else { HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid channel %u MHz\n", __func__, freq); return AH_FALSE; } channelSel = (channelSel << 2) & 0xff; channelSel = ath_hal_reverseBits(channelSel, 8); txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { /* Enable channel spreading for channel 14 */ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); } } else if ((freq % 20) == 0 && freq >= 5120) { channelSel = ath_hal_reverseBits( ((freq - 4800) / 20 << 2), 8); if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) aModeRefSel = ath_hal_reverseBits(3, 2); else aModeRefSel = ath_hal_reverseBits(1, 2); } else if ((freq % 10) == 0) { channelSel = ath_hal_reverseBits( ((freq - 4800) / 10 << 1), 8); if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) aModeRefSel = ath_hal_reverseBits(2, 2); else aModeRefSel = ath_hal_reverseBits(1, 2); } else if ((freq % 5) == 0) { channelSel = ath_hal_reverseBits( (freq - 4800) / 5, 8); aModeRefSel = ath_hal_reverseBits(1, 2); } else { HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid channel %u MHz\n", __func__, freq); return AH_FALSE; } #ifdef ATH_FORCE_BIAS /* FOWL orientation sensitivity workaround */ ar5416ForceBiasCurrent(ah, freq); /* * Antenna Control with forceBias. * This function must be called after ar5416ForceBiasCurrent() and * ar5416SetRfRegs() and ar5416EepromSetBoardValues(). */ ar5416DecreaseChainPower(ah, (HAL_CHANNEL*)chan); #endif reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | (1 << 5) | 0x1; OS_REG_WRITE(ah, AR_PHY(0x37), reg32); AH_PRIVATE(ah)->ah_curchan = chan; #ifdef AH_SUPPORT_DFS if (chan->privFlags & CHANNEL_DFS) { struct ar5416RadarState *rs; u_int8_t index; rs = ar5416GetRadarChanState(ah, &index); if (rs != AH_NULL) { AH5416(ah)->ah_curchanRadIndex = (int16_t) index; } else { HDPRINTF(ah, HAL_DBG_DFS, "%s: Couldn't find radar state information\n", __func__); return AH_FALSE; } } else #endif AH5416(ah)->ah_curchanRadIndex = -1; return AH_TRUE; }
/* * Take the MHz channel value and set the Channel value * * ASSUMES: Writes enabled to analog bus */ static HAL_BOOL ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) { uint32_t channelSel = 0; uint32_t bModeSynth = 0; uint32_t aModeRefSel = 0; uint32_t reg32 = 0; uint16_t freq; CHAN_CENTERS centers; OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq); ar5416GetChannelCenters(ah, chan, ¢ers); freq = centers.synth_center; if (freq < 4800) { uint32_t txctl; if (((freq - 2192) % 5) == 0) { channelSel = ((freq - 672) * 2 - 3040)/10; bModeSynth = 0; } else if (((freq - 2224) % 5) == 0) { channelSel = ((freq - 704) * 2 - 3040) / 10; bModeSynth = 1; } else { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n", __func__, freq); return AH_FALSE; } channelSel = (channelSel << 2) & 0xff; channelSel = ath_hal_reverseBits(channelSel, 8); txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { /* Enable channel spreading for channel 14 */ OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); } } else if ((freq % 20) == 0 && freq >= 5120) { channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8); if (AR_SREV_SOWL_10_OR_LATER(ah)) aModeRefSel = ath_hal_reverseBits(3, 2); else aModeRefSel = ath_hal_reverseBits(1, 2); } else if ((freq % 10) == 0) { channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8); if (AR_SREV_SOWL_10_OR_LATER(ah)) aModeRefSel = ath_hal_reverseBits(2, 2); else aModeRefSel = ath_hal_reverseBits(1, 2); } else if ((freq % 5) == 0) { channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8); aModeRefSel = ath_hal_reverseBits(1, 2); } else { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n", __func__, freq); return AH_FALSE; } reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | (1 << 5) | 0x1; OS_REG_WRITE(ah, AR_PHY(0x37), reg32); AH_PRIVATE(ah)->ah_curchan = chan; return AH_TRUE; }
HAL_BOOL ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan) { struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; HAL_CHANNEL_INTERNAL *ichan; ichan = ath_hal_checkchannel(ah, chan); HALASSERT(ichan != AH_NULL); /* Do initial chipset-specific calibration */ if (! AH5416(ah)->ah_cal_initcal(ah, chan)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: initial chipset calibration did " "not complete in time; noisy environment?\n", __func__); return AH_FALSE; } /* If there's PA Cal, do it */ if (AH5416(ah)->ah_cal_pacal) AH5416(ah)->ah_cal_pacal(ah, AH_TRUE); /* * Do NF calibration after DC offset and other CALs. * Per system engineers, noise floor value can sometimes be 20 dB * higher than normal value if DC offset and noise floor cal are * triggered at the same time. */ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); /* * This may take a while to run; make sure subsequent * calibration routines check that this has completed * before reading the value and triggering a subsequent * calibration. */ /* Initialize list pointers */ cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL; /* * Enable IQ, ADC Gain, ADC DC Offset Cals */ if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) { /* Setup all non-periodic, init time only calibrations */ /* XXX: Init DC Offset not working yet */ #if 0 if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) { INIT_CAL(&cal->adcDcCalInitData); INSERT_CAL(cal, &cal->adcDcCalInitData); } /* Initialize current pointer to first element in list */ cal->cal_curr = cal->cal_list; if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0)) return AH_FALSE; #endif } /* If Cals are supported, add them to list via INIT/INSERT_CAL */ if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) { INIT_CAL(&cal->adcGainCalData); INSERT_CAL(cal, &cal->adcGainCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable ADC Gain Calibration.\n", __func__); } if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) { INIT_CAL(&cal->adcDcCalData); INSERT_CAL(cal, &cal->adcDcCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable ADC DC Calibration.\n", __func__); } if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) { INIT_CAL(&cal->iqCalData); INSERT_CAL(cal, &cal->iqCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable IQ Calibration.\n", __func__); } /* Initialize current pointer to first element in list */ cal->cal_curr = cal->cal_list; /* Kick off measurements for the first cal */ if (cal->cal_curr != AH_NULL) ar5416ResetMeasurement(ah, cal->cal_curr); /* Mark all calibrations on this channel as being invalid */ ichan->calValid = 0; return AH_TRUE; #undef MAX_CAL_CHECK }
/* * Initialize Calibration infrastructure. */ HAL_BOOL ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan) { struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; HAL_CHANNEL_INTERNAL *ichan; ichan = ath_hal_checkchannel(ah, chan); HALASSERT(ichan != AH_NULL); if (AR_SREV_MERLIN_10_OR_LATER(ah)) { /* Enable Rx Filter Cal */ OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); /* Clear the carrier leak cal bit */ OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); /* kick off the cal */ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); /* Poll for offset calibration complete */ if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: offset calibration failed to complete in 1ms; " "noisy environment?\n", __func__); return AH_FALSE; } /* Set the cl cal bit and rerun the cal a 2nd time */ /* Enable Rx Filter Cal */ OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); } /* Calibrate the AGC */ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); /* Poll for offset calibration complete */ if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: offset calibration did not complete in 1ms; " "noisy environment?\n", __func__); return AH_FALSE; } /* * Do NF calibration after DC offset and other CALs. * Per system engineers, noise floor value can sometimes be 20 dB * higher than normal value if DC offset and noise floor cal are * triggered at the same time. */ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); /* Initialize list pointers */ cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL; /* * Enable IQ, ADC Gain, ADC DC Offset Cals */ if (AR_SREV_SOWL_10_OR_LATER(ah)) { /* Setup all non-periodic, init time only calibrations */ /* XXX: Init DC Offset not working yet */ #if 0 if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) { INIT_CAL(&cal->adcDcCalInitData); INSERT_CAL(cal, &cal->adcDcCalInitData); } /* Initialize current pointer to first element in list */ cal->cal_curr = cal->cal_list; if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0)) return AH_FALSE; #endif } /* If Cals are supported, add them to list via INIT/INSERT_CAL */ if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) { INIT_CAL(&cal->adcGainCalData); INSERT_CAL(cal, &cal->adcGainCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable ADC Gain Calibration.\n", __func__); } if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) { INIT_CAL(&cal->adcDcCalData); INSERT_CAL(cal, &cal->adcDcCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable ADC DC Calibration.\n", __func__); } if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) { INIT_CAL(&cal->iqCalData); INSERT_CAL(cal, &cal->iqCalData); HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: enable IQ Calibration.\n", __func__); } /* Initialize current pointer to first element in list */ cal->cal_curr = cal->cal_list; /* Kick off measurements for the first cal */ if (cal->cal_curr != AH_NULL) ar5416ResetMeasurement(ah, cal->cal_curr); /* Mark all calibrations on this channel as being invalid */ ichan->calValid = 0; return AH_TRUE; }