static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS |
AT91C_DDRC2_MD_DDR3_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 |
AT91C_DDRC2_NR_14 |
AT91C_DDRC2_CAS_5 |
AT91C_DDRC2_DIS_DLL_DISABLED |
AT91C_DDRC2_WEAK_STRENGTH_RZQ7 |
AT91C_DDRC2_NB_BANKS_8 |
AT91C_DDRC2_DECOD_INTERLEAVED |
AT91C_DDRC2_UNAL_SUPPORTED);
/*
* According to MT41K128M16 datasheet
* Maximum fresh period: 64ms, refresh count: 8k
*/
#ifdef CONFIG_BUS_SPEED_166MHZ
/* Refresh Timer is (64ms / 8k) * 166MHz = 1297(0x511) */
ddramc_config->rtr = 0x511;
/*
* According to the sama5d2 datasheet and the following values:
* T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
* Warning: note that the values T driftrate and V driftrate are dependent on
* the application environment.
* ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
* If tref is 7.8us, we have: 400000 / 7.8 = 51282(0xC852)
* */
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
/* DDR3 ZQCS */
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(64);
/* Assume timings for 8ns min clock period */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) |
AT91C_DDRC2_TRCD_(3) |
AT91C_DDRC2_TWR_(4) |
AT91C_DDRC2_TRC_(9) |
AT91C_DDRC2_TRP_(3) |
AT91C_DDRC2_TRRD_(4) |
AT91C_DDRC2_TWTR_(4) |
AT91C_DDRC2_TMRD_(4));
ddramc_config->t1pr = (AT91C_DDRC2_TRFC_(27) |
AT91C_DDRC2_TXSNR_(29) |
AT91C_DDRC2_TXSRD_(0) |
AT91C_DDRC2_TXP_(3));
ddramc_config->t2pr = (AT91C_DDRC2_TXARD_(0) |
AT91C_DDRC2_TXARDS_(0) |
AT91C_DDRC2_TRPA_(0) |
AT91C_DDRC2_TRTP_(4) |
AT91C_DDRC2_TFAW_(7));
#else
#error "No CLK setting defined"
#endif
}
static void lpddr2_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_LPDDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_14
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_ZQ_SHORT
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_UNAL_SUPPORTED);
ddramc_config->lpddr2_lpr = AT91C_LPDDRC2_DS(0x03);
/* 90n short calibration: ZQCS */
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(12);
/*
* The MT42128M32 refresh window: 32ms
* Required number of REFRESH commands(MIN): 8192
* (32ms / 8192) * 132MHz = 514 i.e. 0x202
*/
ddramc_config->rtr = 0x202;
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)
| AT91C_DDRC2_TRCD_(2)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(8)
| AT91C_DDRC2_TRP_(2)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(3));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSNR_(18)
| AT91C_DDRC2_TRFC_(17));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(1)
| AT91C_DDRC2_TXARD_(1));
}