static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_14
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_148MHZ)
ddramc_config->rtr = 0x243;
/* One clock cycle @ 148 MHz = 6.7 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(9)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(31)
| AT91C_DDRC2_TRFC_(30));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_170MHZ)
ddramc_config->rtr = 0x229;
/* One clock cycle @ 170 MHz = 5.9 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(7)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(24)
| AT91C_DDRC2_TRFC_(22));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(2)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_176MHZ)
ddramc_config->rtr = 0x2b0;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(25)
| AT91C_DDRC2_TRFC_(23));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(2)
| AT91C_DDRC2_TXARD_(8));
#else
#error "No CLK setting defined"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
| AT91C_DDRC2_NR_13
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_ENRDM_ENABLE
| AT91C_DDRC2_NB_BANKS_8
| AT91C_DDRC2_NDQS_DISABLED
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_133MHZ)
/*
* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
* With a 133 MHz frequency, the refresh timer count register must to be
* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
* or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
*/
ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
| AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TXARDS_(8) /* = TXARD */
| AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
#elif defined(CONFIG_BUS_SPEED_166MHZ)
/*
* The DDR2-SDRAM device requires a refresh of all rows every 64ms.
* ((64ms) / 8192) * 166MHz = 1296 i.e. 0x510
*/
ddramc_config->rtr = 0x510;
/* One clock cycle @ 166 MHz = 6.0 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8) /* 8 * 6 = 48 ns */
| AT91C_DDRC2_TRCD_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TWR_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TRC_(10) /* 10 * 6 = 60 ns */
| AT91C_DDRC2_TRP_(3) /* 3 * 6 = 18 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 6 = 12 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 * 6 = 12ns */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(23) /* 23 * 6 = 138 ns */
| AT91C_DDRC2_TRFC_(22)); /* 22 * 6 = 132 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8) /* 45 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 * 6 = 15ns */
| AT91C_DDRC2_TRPA_(3) /* 15 ns */
| AT91C_DDRC2_TXARDS_(8) /* = TXARD */
| AT91C_DDRC2_TXARD_(8)); /* 8 clock cycles */
#else
#error "No bus clock provided!"
#endif
}
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 colum bit */
| AT91C_DDRC2_NR_13
| AT91C_DDRC2_CAS_3
| AT91C_DDRC2_WEAK_STRENGTH_RZQ7
| AT91C_DDRC2_DLL_RESET_DISABLED
| AT91C_DDRC2_DIS_DLL_DISABLED
| AT91C_DDRC2_NB_BANKS_4
| AT91C_DDRC2_DECOD_INTERLEAVED
| AT91C_DDRC2_UNAL_SUPPORTED);
#if defined(CONFIG_BUS_SPEED_176MHZ)
ddramc_config->rtr = 0x55f;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(10)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(21)
| AT91C_DDRC2_TRFC_(19));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(8)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(8));
#elif defined(CONFIG_BUS_SPEED_200MHZ)
ddramc_config->rtr = 0x61b;
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(8)
| AT91C_DDRC2_TRCD_(3)
| AT91C_DDRC2_TWR_(3)
| AT91C_DDRC2_TRC_(11)
| AT91C_DDRC2_TRP_(3)
| AT91C_DDRC2_TRRD_(2)
| AT91C_DDRC2_TWTR_(2)
| AT91C_DDRC2_TMRD_(2));
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)
| AT91C_DDRC2_TXSRD_(200)
| AT91C_DDRC2_TXSNR_(23)
| AT91C_DDRC2_TRFC_(21));
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(9)
| AT91C_DDRC2_TRTP_(2)
| AT91C_DDRC2_TRPA_(3)
| AT91C_DDRC2_TXARDS_(8)
| AT91C_DDRC2_TXARD_(8));
#else
#error "No CLK setting defined"
#endif
}
