void hw_init(void)
{
/* Disable watchdog */
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDT + WDTC_MR);
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
/* pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); */
/* Enable External Reset */
writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR);
/* Initialize matrix */
writel((readl(AT91C_BASE_MATRIX + MATRIX_SCFG3) & (~AT91C_MATRIX_SLOT_CYCLE))
| AT91C_MATRIX_SLOT_CYCLE_(0x40),
AT91C_BASE_MATRIX + MATRIX_SCFG3);
#ifdef CONFIG_DEBUG
/* Initialize dbgu */
initialize_dbgu();
#endif
#ifdef CONFIG_SDRAM
/* Initlialize sdram controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
static void at91_matrix_hw_init(void)
{
unsigned int reg;
reg = matrix_readl(MATRIX_SCFG0);
reg |= AT91C_MATRIX_ARBT_FIXED_PRIORITY;
reg |= AT91C_MATRIX_FIXED_DEFMSTR_ARM926D;
matrix_writel(reg, MATRIX_SCFG0); /* ROM */
reg = matrix_readl(MATRIX_SCFG4);
reg |= AT91C_MATRIX_ARBT_FIXED_PRIORITY;
reg |= AT91C_MATRIX_FIXED_DEFMSTR_ARM926D;
reg |= AT91C_MATRIX_SLOT_CYCLE_(0x40);
matrix_writel(reg, MATRIX_SCFG4); /* EBI0 */
}
static void at91_matrix_hw_init(void)
{
unsigned int reg;
reg = matrix_readl(MATRIX_SCFG3);
reg &= ~AT91C_MATRIX_SLOT_CYCLE;
reg |= AT91C_MATRIX_SLOT_CYCLE_(0x40);
matrix_writel(reg, MATRIX_SCFG3);
reg = matrix_readl(MATRIX_SCFG0);
reg |= AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR;
reg |= AT91C_MATRIX_FIXED_DEFMSTR_ARM926D;
matrix_writel(reg, MATRIX_SCFG0);
reg = matrix_readl(MATRIX_SCFG3);
reg |= AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR;
reg |= AT91C_MATRIX_FIXED_DEFMSTR_ARM926D;
matrix_writel(reg, MATRIX_SCFG3);
}
static void at91_matrix_hw_init(void)
{
/* Bus Matrix Master Configuration Register */
matrix_writel(AT91C_MATRIX_ULBT_16_BEAT, MATRIX_MCFG0); /* OHCI */
matrix_writel(AT91C_MATRIX_ULBT_8_BEAT, MATRIX_MCFG1); /* ISI */
matrix_writel(AT91C_MATRIX_ULBT_8_BEAT, MATRIX_MCFG2); /* 2D */
matrix_writel(AT91C_MATRIX_ULBT_8_BEAT, MATRIX_MCFG3); /* DMAC */
matrix_writel(AT91C_MATRIX_ULBT_4_BEAT, MATRIX_MCFG4); /* MACB */
matrix_writel(AT91C_MATRIX_ULBT_16_BEAT, MATRIX_MCFG5); /* LCDC */
matrix_writel(AT91C_MATRIX_ULBT_SINGLE_ACCESS, MATRIX_MCFG6); /* PDC */
matrix_writel(AT91C_MATRIX_ULBT_8_BEAT, MATRIX_MCFG7); /* DBUS */
matrix_writel(AT91C_MATRIX_ULBT_4_BEAT, MATRIX_MCFG8); /* IBUS */
/* Bus Matrix Slave Configuration Registers */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_ARM926I
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(32)),
MATRIX_SCFG0); /* ROM */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_EMAC
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(32)),
MATRIX_SCFG1); /* RAM80K */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_USB
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(16)),
MATRIX_SCFG2); /* RAM16K */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_PDC
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(4)),
MATRIX_SCFG3); /* PERIPHERALS */
matrix_writel((AT91C_MATRIX_ARBT_ROUND_ROBIN
| AT91C_MATRIX_FIXED_DEFMSTR_ARM926I
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(32)),
MATRIX_SCFG4); /* EBI0 */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_LCDC
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(64)),
MATRIX_SCFG5); /* EBI1 */
matrix_writel((AT91C_MATRIX_ARBT_FIXED_PRIORITY
| AT91C_MATRIX_FIXED_DEFMSTR_ARM926D
| AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
| AT91C_MATRIX_SLOT_CYCLE_(4)),
MATRIX_SCFG6); /* APB */
/* ROM */
matrix_writel((AT91C_MATRIX_M0PR_(1)
| AT91C_MATRIX_M1PR_(0)
| AT91C_MATRIX_M2PR_(2)
| AT91C_MATRIX_M3PR_(1)
| AT91C_MATRIX_M4PR_(0)
| AT91C_MATRIX_M5PR_(3)
| AT91C_MATRIX_M6PR_(2)
| AT91C_MATRIX_M7PR_(3)),
MATRIX_PRAS0);
matrix_writel(AT91C_MATRIX_M8PR_(0),
MATRIX_PRBS0);
/* RAM80K */
matrix_writel((AT91C_MATRIX_M0PR_(1)
| AT91C_MATRIX_M1PR_(2)
| AT91C_MATRIX_M2PR_(1)
| AT91C_MATRIX_M3PR_(3)
| AT91C_MATRIX_M4PR_(0)
| AT91C_MATRIX_M5PR_(0)
| AT91C_MATRIX_M6PR_(3)
| AT91C_MATRIX_M7PR_(0)),
MATRIX_PRAS1);
matrix_writel(AT91C_MATRIX_M8PR_(2),
MATRIX_PRBS1);
/* RAM16K */
matrix_writel((AT91C_MATRIX_M0PR_(1)
| AT91C_MATRIX_M1PR_(0)
| AT91C_MATRIX_M2PR_(2)
| AT91C_MATRIX_M3PR_(1)
| AT91C_MATRIX_M4PR_(0)
| AT91C_MATRIX_M5PR_(3)
| AT91C_MATRIX_M6PR_(3)
| AT91C_MATRIX_M7PR_(2)),
MATRIX_PRAS2);
matrix_writel(AT91C_MATRIX_M8PR_(0),
MATRIX_PRBS2);
/* PERIPHERALS */
matrix_writel((AT91C_MATRIX_M0PR_(0)
| AT91C_MATRIX_M1PR_(1)
| AT91C_MATRIX_M2PR_(0)
| AT91C_MATRIX_M3PR_(2)
| AT91C_MATRIX_M4PR_(1)
| AT91C_MATRIX_M5PR_(0)
| AT91C_MATRIX_M6PR_(3)
| AT91C_MATRIX_M7PR_(2)),
MATRIX_PRAS3);
matrix_writel(AT91C_MATRIX_M8PR_(3),
MATRIX_PRBS3);
#if defined(CONFIG_PSRAM)
/* EBI0 */
matrix_writel((AT91C_MATRIX_M0PR_(2)
| AT91C_MATRIX_M1PR_(1)
| AT91C_MATRIX_M2PR_(1)
| AT91C_MATRIX_M3PR_(3)
| AT91C_MATRIX_M4PR_(0)
| AT91C_MATRIX_M5PR_(3)
| AT91C_MATRIX_M6PR_(0)
| AT91C_MATRIX_M7PR_(0)),
MATRIX_PRAS4);
matrix_writel(AT91C_MATRIX_M8PR_(2),
MATRIX_PRBS4);
#else
/* EBI0 */
matrix_writel((AT91C_MATRIX_M0PR_(1)
| AT91C_MATRIX_M1PR_(3)
| AT91C_MATRIX_M2PR_(0)
| AT91C_MATRIX_M3PR_(2)
| AT91C_MATRIX_M4PR_(3)
| AT91C_MATRIX_M5PR_(0)
| AT91C_MATRIX_M6PR_(0)
| AT91C_MATRIX_M7PR_(1)),
MATRIX_PRAS4);
matrix_writel(AT91C_MATRIX_M8PR_(2),
MATRIX_PRBS4);
#endif /* #if defined(CONFIG_PSRAM) */
/* EBI1 */
matrix_writel((AT91C_MATRIX_M0PR_(0)
| AT91C_MATRIX_M1PR_(1)
| AT91C_MATRIX_M2PR_(0)
| AT91C_MATRIX_M3PR_(0)
| AT91C_MATRIX_M4PR_(3)
| AT91C_MATRIX_M5PR_(2)
| AT91C_MATRIX_M6PR_(3)
| AT91C_MATRIX_M7PR_(2)),
MATRIX_PRAS5);
matrix_writel(AT91C_MATRIX_M8PR_(1),
MATRIX_PRBS5);
/* APB */
matrix_writel((AT91C_MATRIX_M0PR_(1)
| AT91C_MATRIX_M1PR_(0)
| AT91C_MATRIX_M2PR_(2)
| AT91C_MATRIX_M3PR_(1)
| AT91C_MATRIX_M4PR_(0)
| AT91C_MATRIX_M5PR_(0)
| AT91C_MATRIX_M6PR_(3)
| AT91C_MATRIX_M7PR_(3)),
MATRIX_PRAS4);
matrix_writel(AT91C_MATRIX_M8PR_(2),
MATRIX_PRBS4);
}
