static void at91_dbgu_hw_init(void)
{
const struct pio_desc dbgu_pins[] = {
{"RXD", AT91C_PIN_PE(16), 0, PIO_DEFAULT, PIO_PERIPH_B},
{"TXD", AT91C_PIN_PE(17), 0, PIO_DEFAULT, PIO_PERIPH_B},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(dbgu_pins);
pmc_enable_periph_clock(AT91C_ID_PIOE);
pmc_enable_periph_clock(AT91C_ID_USART3);
}
void nandflash_hw_init(void)
{
/* Configure nand pins */
const struct pio_desc nand_pins[] = {
{"NANDALE", AT91C_PIN_PE(21), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the nand controller pins*/
pio_configure(nand_pins);
writel((1 << AT91C_ID_PIOE), (PMC_PCER + AT91C_BASE_PMC));
/* Enable the clock */
writel(1 << AT91C_ID_SMC, (PMC_PCER + AT91C_BASE_PMC));
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91C_SMC_SETUP_NWE(1)
| AT91C_SMC_SETUP_NCS_WR(1)
| AT91C_SMC_SETUP_NRD(2)
| AT91C_SMC_SETUP_NCS_RD(1),
(ATMEL_BASE_SMC + SMC_SETUP3));
writel(AT91C_SMC_PULSE_NWE(5)
| AT91C_SMC_PULSE_NCS_WR(7)
| AT91C_SMC_PULSE_NRD(5)
| AT91C_SMC_PULSE_NCS_RD(7),
(ATMEL_BASE_SMC + SMC_PULSE3));
writel(AT91C_SMC_CYCLE_NWE(8)
| AT91C_SMC_CYCLE_NRD(9),
(ATMEL_BASE_SMC + SMC_CYCLE3));
writel(AT91C_SMC_TIMINGS_TCLR(3)
| AT91C_SMC_TIMINGS_TADL(10)
| AT91C_SMC_TIMINGS_TAR(3)
| AT91C_SMC_TIMINGS_TRR(4)
| AT91C_SMC_TIMINGS_TWB(5)
| AT91C_SMC_TIMINGS_RBNSEL(3)
| AT91C_SMC_TIMINGS_NFSEL,
(ATMEL_BASE_SMC + SMC_TIMINGS3));
writel(AT91C_SMC_MODE_READMODE_NRD_CTRL
| AT91C_SMC_MODE_WRITEMODE_NWE_CTRL
| AT91C_SMC_MODE_EXNWMODE_DISABLED
| AT91C_SMC_MODE_DBW_8
| AT91C_SMC_MODE_TDF_CYCLES(1),
(ATMEL_BASE_SMC + SMC_MODE3));
}
void nandflash_hw_init(void)
{
const struct pio_desc nand_pins[] = {
{"NANDALE", AT91C_PIN_PE(21), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOE);
pio_configure(nand_pins);
pmc_enable_periph_clock(AT91C_ID_SMC);
writel(AT91C_SMC_SETUP_NWE(1)
| AT91C_SMC_SETUP_NCS_WR(1)
| AT91C_SMC_SETUP_NRD(2)
| AT91C_SMC_SETUP_NCS_RD(1),
(ATMEL_BASE_SMC + SMC_SETUP3));
writel(AT91C_SMC_PULSE_NWE(5)
| AT91C_SMC_PULSE_NCS_WR(7)
| AT91C_SMC_PULSE_NRD(5)
| AT91C_SMC_PULSE_NCS_RD(7),
(ATMEL_BASE_SMC + SMC_PULSE3));
writel(AT91C_SMC_CYCLE_NWE(8)
| AT91C_SMC_CYCLE_NRD(9),
(ATMEL_BASE_SMC + SMC_CYCLE3));
writel(AT91C_SMC_TIMINGS_TCLR(3)
| AT91C_SMC_TIMINGS_TADL(10)
| AT91C_SMC_TIMINGS_TAR(3)
| AT91C_SMC_TIMINGS_TRR(4)
| AT91C_SMC_TIMINGS_TWB(5)
| AT91C_SMC_TIMINGS_RBNSEL(3)
| AT91C_SMC_TIMINGS_NFSEL,
(ATMEL_BASE_SMC + SMC_TIMINGS3));
writel(AT91C_SMC_MODE_READMODE_NRD_CTRL
| AT91C_SMC_MODE_WRITEMODE_NWE_CTRL
| AT91C_SMC_MODE_EXNWMODE_DISABLED
| AT91C_SMC_MODE_DBW_8
| AT91C_SMC_MODE_TDF_CYCLES(1),
(ATMEL_BASE_SMC + SMC_MODE3));
}
static void one_wire_hw_init(void)
{
const struct pio_desc one_wire_pio[] = {
{"1-Wire", AT91C_PIN_PE(25), 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
writel((1 << AT91C_ID_PIOE), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(one_wire_pio);
}
static void one_wire_hw_init(void)
{
const struct pio_desc one_wire_pio[] = {
{"1-Wire", AT91C_PIN_PE(25), 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOE);
pio_configure(one_wire_pio);
}
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCI1_CK", AT91C_PIN_PE(18), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"MCI1_CDA", AT91C_PIN_PE(19), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"MCI1_DA0", AT91C_PIN_PE(20), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"MCI1_DA1", AT91C_PIN_PE(21), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"MCI1_DA2", AT91C_PIN_PE(22), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"MCI1_DA3", AT91C_PIN_PE(23), 0, PIO_DEFAULT, PIO_PERIPH_C},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
pio_configure(mci_pins);
pmc_enable_periph_clock(AT91C_ID_PIOE);
pmc_enable_periph_clock(AT91C_ID_HSMCI1);
}