/* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct at91_wdt_priv *priv = dev_get_priv(dev); u64 timeout; u32 ticks; /* Calculate timeout in seconds and the resulting ticks */ timeout = timeout_ms; do_div(timeout, 1000); timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT); ticks = WDT_SEC2TICKS(timeout); /* Check if disabled */ if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } /* * All counting occurs at SLOW_CLOCK / 128 = 256 Hz * * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ | AT91_WDT_MR_WDV(ticks); /* timer value */ writel(priv->regval, priv->regs + AT91_WDT_MR); return 0; }
/* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ static int at91_wdt_settimeout(unsigned int timeout) { unsigned int reg; at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; /* Check if disabled */ if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } /* * All counting occurs at SLOW_CLOCK / 128 = 256 Hz * * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ | AT91_WDT_MR_WDV(timeout); /* timer value */ writel(reg, &wd->mr); return 0; }