static void
ahci_em_setleds(device_t dev, int c)
{
struct ahci_enclosure *enc;
int timeout;
int16_t val;
enc = device_get_softc(dev);
val = 0;
if (enc->status[c][2] & 0x80) /* Activity */
val |= (1 << 0);
if (enc->status[c][2] & SESCTL_RQSID) /* Identification */
val |= (1 << 3);
else if (enc->status[c][3] & SESCTL_RQSFLT) /* Fault */
val |= (1 << 6);
else if (enc->status[c][1] & 0x02) /* Rebuild */
val |= (1 << 6) | (1 << 3);
timeout = 10000;
while (ATA_INL(enc->r_memc, 0) & (AHCI_EM_TM | AHCI_EM_RST) &&
--timeout > 0)
DELAY(100);
if (timeout == 0)
device_printf(dev, "Transmit timeout\n");
ATA_OUTL(enc->r_memt, 0, (1 << 8) | (0 << 16) | (0 << 24));
ATA_OUTL(enc->r_memt, 4, c | (0 << 8) | (val << 16));
ATA_OUTL(enc->r_memc, 0, AHCI_EM_TM);
}
static int
ata_nvidia_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
if (ctlr->chip->cfg1 & NVAHCI) {
ctlr->ch_attach = ata_nvidia_ch_attach_dumb;
ctlr->setmode = ata_sata_setmode;
} else if (ctlr->chip->max_dma >= ATA_SA150) {
if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
ctlr->r_type2 = SYS_RES_IOPORT;
else
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))) {
int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
ctlr->ch_attach = ata_nvidia_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_nvidia_reset;
/* enable control access */
pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
/* MCP55 seems to need some time to allow r_res2 read. */
DELAY(10);
if (ctlr->chip->cfg1 & NVQ) {
/* clear interrupt status */
ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
/* enable device and PHY state change interrupts */
ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
/* disable NCQ support */
ATA_OUTL(ctlr->r_res2, 0x0400,
ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
}
else {
/* clear interrupt status */
ATA_OUTB(ctlr->r_res2, offset, 0xff);
/* enable device and PHY state change interrupts */
ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
}
}
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
}
else {
/* disable prefetch, postwrite */
pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
ctlr->setmode = ata_nvidia_setmode;
}
return 0;
}
static int
imx6_ahci_phy_write(struct ahci_controller* sc, uint32_t addr,
uint16_t data)
{
int error;
error = imx6_ahci_phy_addr(sc, addr);
if (error != 0) {
device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
__FUNCTION__);
return (error);
}
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
if (error != 0) {
device_printf(sc->dev,
"%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
return (error);
}
if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
device_printf(sc->dev,
"%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
return (error);
}
if ((addr == SATA_PHY_CLOCK_RESET) && data) {
/* we can't check ACK after RESET */
ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
return (0);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
if (error != 0) {
device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n",
__FUNCTION__);
return (error);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
if (error != 0) {
device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n",
__FUNCTION__);
return (error);
}
return (0);
}
static int
ata_nvidia_status(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
u_int32_t istatus;
/* get interrupt status */
if (ctlr->chip->cfg1 & NVQ)
istatus = ATA_INL(ctlr->r_res2, offset);
else
istatus = ATA_INB(ctlr->r_res2, offset);
/* do we have any PHY events ? */
if (istatus & (0x0c << shift))
ata_sata_phy_check_events(dev, -1);
/* clear interrupt(s) */
if (ctlr->chip->cfg1 & NVQ)
ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
else
ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
/* do we have any device action ? */
return (istatus & (0x01 << shift));
}
static int
imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
{
uint32_t v;
int timeout;
bool state;
v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
if (on) {
v |= bitmask;
} else {
v &= ~bitmask;
}
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
for (timeout = 5000; timeout > 0; --timeout) {
v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
state = (v & SATA_P0PHYSR_CR_ACK) == SATA_P0PHYSR_CR_ACK;
if(state == on) {
break;
}
DELAY(100);
}
if (timeout > 0) {
return (0);
}
return (ETIMEDOUT);
}
static int
imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
{
int error;
DELAY(100);
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
if (error != 0) {
device_printf(sc->dev,
"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n",
__FUNCTION__);
return (error);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
if (error != 0) {
device_printf(sc->dev,
"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n",
__FUNCTION__);
return (error);
}
return (0);
}
static void inline
ahci_clr(struct resource *m, bus_size_t off, uint32_t clr)
{
uint32_t val = ATA_INL(m, off);
val &= ~clr;
ATA_OUTL(m, off, val);
}
static void inline
ahci_set(struct resource *m, bus_size_t off, uint32_t set)
{
uint32_t val = ATA_INL(m, off);
val |= set;
ATA_OUTL(m, off, val);
}
static int
mvs_suspend(device_t dev)
{
struct mvs_controller *ctlr = device_get_softc(dev);
bus_generic_suspend(dev);
/* Mask chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
return 0;
}
static int
ata_sii_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
int i;
for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
ch->r_io[i].res = ctlr->r_res2;
ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
}
ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
ata_default_registers(dev);
ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
if (ctlr->chip->max_dma >= ATA_SA150) {
ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SERROR].res = ctlr->r_res2;
ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
ch->flags |= ATA_KNOWN_PRESENCE;
/* enable PHY state change interrupt */
ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
}
if (ctlr->chip->cfg2 & SII_BUG) {
/* work around errata in early chips */
ch->dma.boundary = 8192;
ch->dma.segsize = 15 * DEV_BSIZE;
}
ata_pci_hw(dev);
ch->hw.status = ata_sii_status;
if (ctlr->chip->cfg2 & SII_SETCLK)
ch->flags |= ATA_CHECKS_CABLE;
ata_pci_dmainit(dev);
return 0;
}
static int
tegra_ahci_suspend(device_t dev)
{
struct tegra_ahci_sc *sc = device_get_softc(dev);
bus_generic_suspend(dev);
/* Disable interupts, so the state change(s) doesn't trigger. */
ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC,
ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
return (0);
}
static int
mvs_ctlr_setup(device_t dev)
{
struct mvs_controller *ctlr = device_get_softc(dev);
int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
/* Mask chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
/* Clear HC interrupts */
ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000);
/* Clear chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0);
/* Configure per-HC CCC */
if (ccc && bootverbose) {
device_printf(dev,
"CCC with %dus/%dcmd enabled\n",
ctlr->ccc, ctlr->cccc);
}
ccc *= 150;
ATA_OUTL(ctlr->r_mem, HC_ICT, cccc);
ATA_OUTL(ctlr->r_mem, HC_ITT, ccc);
if (ccc)
ccim |= IC_HC0_COAL_DONE;
/* Enable chip interrupts */
ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE :
(IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) |
(IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels)));
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
return (0);
}
static void
ahci_a10_ch_start(struct ahci_channel *ch)
{
uint32_t reg;
/*
* Magical values from Allwinner SDK, setup the DMA before start
* operations on this channel.
*/
reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
reg &= ~0xff00;
reg |= 0x4400;
ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);
}
static int
ata_siiprb_issue_cmd(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
u_int64_t prb_bus = ch->dma.work_bus;
u_int32_t status;
int offset = ch->unit * 0x2000;
int timeout;
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
/* issue command to chip */
ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
/* poll for command finished */
for (timeout = 0; timeout < 10000; timeout++) {
DELAY(1000);
if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
break;
}
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
// SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
if (timeout >= 1000)
return EIO;
if (bootverbose)
device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
timeout, status);
return 0;
}
static int
ata_cyrix_setmode(device_t dev, int target, int mode)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int devno = (ch->unit << 1) + target;
int piomode;
static const uint32_t piotiming[] =
{ 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
static const uint32_t dmatiming[] =
{ 0x00077771, 0x00012121, 0x00002020 };
static const uint32_t udmatiming[] =
{ 0x00921250, 0x00911140, 0x00911030 };
mode = min(mode, ATA_UDMA2);
/* dont try to set the mode if we dont have the resource */
if (ctlr->r_res1) {
if (mode >= ATA_UDMA0) {
/* Set UDMA timings, and PIO4. */
ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
piomode = ATA_PIO4;
} else if (mode >= ATA_WDMA0) {
/* Set WDMA timings, and respective PIO mode. */
ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
(mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
} else
piomode = mode;
/* Set PIO mode calculated above. */
ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
0x20 + (devno << 3), piotiming[ata_mode2idx(piomode)]);
}
return (mode);
}
static void
mvs_edma(device_t dev, device_t child, int mode)
{
struct mvs_controller *ctlr = device_get_softc(dev);
int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
int bit = IC_DONE_IRQ << (unit * 2);
if (ctlr->ccc == 0)
return;
/* CCC is not working for non-EDMA mode. Unmask device interrupts. */
mtx_lock(&ctlr->mtx);
if (mode == MVS_EDMA_OFF)
ctlr->pmim |= bit;
else
ctlr->pmim &= ~bit;
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
mtx_unlock(&ctlr->mtx);
}
static void
ata_sii_reset(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
uint32_t val;
/* Apply R_ERR on DMA activate FIS errata workaround. */
val = ATA_INL(ctlr->r_res2, 0x14c + offset);
if ((val & 0x3) == 0x1)
ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
if (ata_sata_phy_reset(dev, -1, 1))
ata_generic_reset(dev);
else
ch->devices = 0;
}
static int
ahci_em_reset(device_t dev)
{
struct ahci_enclosure *enc;
int i, timeout;
enc = device_get_softc(dev);
ATA_OUTL(enc->r_memc, 0, AHCI_EM_RST);
timeout = 1000;
while ((ATA_INL(enc->r_memc, 0) & AHCI_EM_RST) &&
--timeout > 0)
DELAY(1000);
if (timeout == 0) {
device_printf(dev, "EM timeout\n");
return (1);
}
for (i = 0; i < enc->channels; i++)
ahci_em_setleds(dev, i);
return (0);
}
static int
ata_siiprb_status(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
int offset = ch->unit * 0x2000;
if (action & (1 << ch->unit)) {
u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
/* do we have any PHY events ? */
ata_sata_phy_check_events(dev, -1);
/* clear interrupt(s) */
ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
/* do we have any device action ? */
return (istatus & 0x00000003);
}
return 0;
}
/*
* Common case interrupt handler.
*/
static void
mvs_intr(void *data)
{
struct mvs_controller *ctlr = data;
struct mvs_intr_arg arg;
void (*function)(void *);
int p, chan_num;
u_int32_t ic, aic;
ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC);
if ((ic & IC_HC0) == 0)
return;
/* Acknowledge interrupts of this HC. */
aic = 0;
/* Processing interrupts from each initialized channel */
for (chan_num = 0; chan_num < ctlr->channels; chan_num++) {
if (ic & (IC_DONE_IRQ << (chan_num * 2)))
aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num);
}
if (ic & IC_HC0_COAL_DONE)
aic |= HC_IC_COAL;
ATA_OUTL(ctlr->r_mem, HC_IC, ~aic);
/* Call per-port interrupt handler. */
for (p = 0; p < ctlr->channels; p++) {
arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
if ((arg.cause != 0) &&
(function = ctlr->interrupt[p].function)) {
arg.arg = ctlr->interrupt[p].argument;
function(&arg);
}
ic >>= 2;
}
}
/*
* Common case interrupt handler.
*/
static void
mvs_intr(void *data)
{
struct mvs_controller *ctlr = data;
struct mvs_intr_arg arg;
void (*function)(void *);
int p;
u_int32_t ic, aic;
ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC);
if ((ic & IC_HC0) == 0)
return;
/* Acknowledge interrupts of this HC. */
aic = 0;
if (ic & (IC_DONE_IRQ << 0))
aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
if (ic & (IC_DONE_IRQ << 2))
aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
if (ic & (IC_DONE_IRQ << 4))
aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
if (ic & (IC_DONE_IRQ << 6))
aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
if (ic & IC_HC0_COAL_DONE)
aic |= HC_IC_COAL;
ATA_OUTL(ctlr->r_mem, HC_IC, ~aic);
/* Call per-port interrupt handler. */
for (p = 0; p < ctlr->channels; p++) {
arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
if ((arg.cause != 0) &&
(function = ctlr->interrupt[p].function)) {
arg.arg = ctlr->interrupt[p].argument;
function(&arg);
}
ic >>= 2;
}
}
static void
ahci_a10_phy_reset(device_t dev)
{
uint32_t to, val;
struct ahci_controller *ctlr = device_get_softc(dev);
/*
* Here start the the magic -- most of the comments are based
* on guesswork, names of routines and printf error
* messages. The code works, but it will do that even if the
* comments are 100% BS.
*/
/*
* Lock out other access while we initialize. Or at least that
* seems to be the case based on Linux SDK #defines. Maybe this
* put things into reset?
*/
ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0);
DELAY(100);
/*
* Set bit 19 in PHYCS1R. Guessing this disables driving the PHY
* port for a bit while we reset things.
*/
ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
/*
* Frob PHYCS0R...
*/
ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
~PHYCS0R_UF2_MASK,
PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18);
/*
* Set three fields in PHYCS1R
*/
ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R,
~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK),
PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT);
/*
* Two more mystery bits in PHYCS1R. -- can these be combined above?
*/
ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28);
/*
* Now clear that first mysery bit. Perhaps this starts
* driving the PHY again so we can power it up and start
* talking to the SATA drive, if any below.
*/
ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
/*
* Frob PHYCS0R again...
*/
ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT);
/*
* Frob PHYCS2R, because 25 means something?
*/
ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK,
PHYCS2R_UF1_INIT);
DELAY(100); /* WAG */
/*
* Turn on the power to the PHY and wait for it to report back
* good?
*/
ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE);
for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R);
if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD)
break;
DELAY(10);
}
if (to == 0 && bootverbose)
device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val);
/*
* Calibrate the clocks between the device and the host. This appears
* to be an automated process that clears the bit when it is done.
*/
ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE);
for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R);
if ((val & PHYCS2R_CALIBRATE) == 0)
break;
DELAY(10);
}
if (to == 0 && bootverbose)
device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val);
/*
* OK, let things settle down a bit.
*/
DELAY(1000);
/*
* Go back into normal mode now that we've calibrated the PHY.
*/
ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7);
}
static int
imx6_ahci_attach(device_t dev)
{
struct ahci_controller* ctlr;
uint16_t pllstat;
uint32_t v;
int error, timeout;
ctlr = device_get_softc(dev);
/* Power up the controller and phy. */
error = imx6_ccm_sata_enable();
if (error != 0) {
device_printf(dev, "error enabling controller and phy\n");
return (error);
}
ctlr->vendorid = 0;
ctlr->deviceid = 0;
ctlr->subvendorid = 0;
ctlr->subdeviceid = 0;
ctlr->numirqs = 1;
ctlr->r_rid = 0;
if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&ctlr->r_rid, RF_ACTIVE)) == NULL) {
return (ENXIO);
}
v = imx_iomux_gpr_get(IOMUX_GPR13);
/* Clear out existing values; these numbers are bitmasks. */
v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
IOMUX_GPR13_SATA_PHY_7(0x1f) |
IOMUX_GPR13_SATA_PHY_6(7) |
IOMUX_GPR13_SATA_SPEED(1) |
IOMUX_GPR13_SATA_PHY_5(1) |
IOMUX_GPR13_SATA_PHY_4(7) |
IOMUX_GPR13_SATA_PHY_3(0xf) |
IOMUX_GPR13_SATA_PHY_2(0x1f) |
IOMUX_GPR13_SATA_PHY_1(1) |
IOMUX_GPR13_SATA_PHY_0(1));
/* setting */
v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
imx_iomux_gpr_set(IOMUX_GPR13, v);
/* phy reset */
error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET,
SATA_PHY_CLOCK_RESET_RST);
if (error != 0) {
device_printf(dev, "cannot reset PHY\n");
goto fail;
}
for (timeout = 50; timeout > 0; --timeout) {
DELAY(100);
error = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT,
&pllstat);
if (error != 0) {
device_printf(dev, "cannot read LANE0 status\n");
goto fail;
}
if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) {
break;
}
}
if (timeout <= 0) {
device_printf(dev, "time out reading LANE0 status\n");
error = ETIMEDOUT;
goto fail;
}
/* Support Staggered Spin-up */
v = ATA_INL(ctlr->r_mem, AHCI_CAP);
ATA_OUTL(ctlr->r_mem, AHCI_CAP, v | AHCI_CAP_SSS);
/* Ports Implemented. must set 1 */
v = ATA_INL(ctlr->r_mem, AHCI_PI);
ATA_OUTL(ctlr->r_mem, AHCI_PI, v | (1 << 0));
/* set 1ms-timer = AHB clock / 1000 */
ATA_OUTL(ctlr->r_mem, SATA_TIMER1MS,
imx_ccm_ahb_hz() / 1000);
/*
* Note: ahci_attach will release ctlr->r_mem on errors automatically
*/
return (ahci_attach(dev));
fail:
bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
return (error);
}
int
ata_sii_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
switch (ctlr->chip->cfg1) {
case SII_PRBIO:
ctlr->r_type1 = SYS_RES_MEMORY;
ctlr->r_rid1 = PCIR_BAR(0);
if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
&ctlr->r_rid1, RF_ACTIVE)))
return ENXIO;
ctlr->r_rid2 = PCIR_BAR(2);
ctlr->r_type2 = SYS_RES_MEMORY;
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))){
bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
return ENXIO;
}
#ifdef __sparc64__
if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
BUS_SPACE_MAP_LINEAR, NULL)) {
bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
ctlr->r_res1);
bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
ctlr->r_res2);
return (ENXIO);
}
#endif
ctlr->ch_attach = ata_siiprb_ch_attach;
ctlr->ch_detach = ata_siiprb_ch_detach;
ctlr->reset = ata_siiprb_reset;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
/* reset controller */
ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
DELAY(10000);
ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
break;
case SII_MEMIO:
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))){
if (ctlr->chip->chipid != ATA_SII0680 ||
(pci_read_config(dev, 0x8a, 1) & 1))
return ENXIO;
}
if (ctlr->chip->cfg2 & SII_SETCLK) {
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
pci_write_config(dev, 0x8a,
(pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
device_printf(dev, "%s could not set ATA133 clock\n",
ctlr->chip->text);
}
/* if we have 4 channels enable the second set */
if (ctlr->chip->cfg2 & SII_4CH) {
ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
ctlr->channels = 4;
}
/* dont block interrupts from any channel */
pci_write_config(dev, 0x48,
(pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
/* enable PCI interrupt as BIOS might not */
pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
if (ctlr->r_res2) {
ctlr->ch_attach = ata_sii_ch_attach;
ctlr->ch_detach = ata_sii_ch_detach;
}
if (ctlr->chip->max_dma >= ATA_SA150) {
ctlr->reset = ata_sii_reset;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
}
else
ctlr->setmode = ata_sii_setmode;
break;
default:
if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
device_printf(dev, "HW has secondary channel disabled\n");
ctlr->channels = 1;
}
/* enable interrupt as BIOS might not */
pci_write_config(dev, 0x71, 0x01, 1);
ctlr->ch_attach = ata_cmd_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->setmode = ata_cmd_setmode;
break;
}
return 0;
}
int
ata_sii_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
switch (ctlr->chip->cfg1) {
case SII_MEMIO:
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))){
if (ctlr->chip->chipid != ATA_SII0680 ||
(pci_read_config(dev, 0x8a, 1) & 1))
return ENXIO;
}
if (ctlr->chip->cfg2 & SII_SETCLK) {
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
pci_write_config(dev, 0x8a,
(pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
device_printf(dev, "%s could not set ATA133 clock\n",
ctlr->chip->text);
}
/* if we have 4 channels enable the second set */
if (ctlr->chip->cfg2 & SII_4CH) {
ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
ctlr->channels = 4;
}
/* dont block interrupts from any channel */
pci_write_config(dev, 0x48,
(pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
/* enable PCI interrupt as BIOS might not */
pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
if (ctlr->r_res2) {
ctlr->ch_attach = ata_sii_ch_attach;
ctlr->ch_detach = ata_sii_ch_detach;
}
if (ctlr->chip->max_dma >= ATA_SA150) {
ctlr->reset = ata_sii_reset;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
}
else
ctlr->setmode = ata_sii_setmode;
break;
default:
if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
device_printf(dev, "HW has secondary channel disabled\n");
ctlr->channels = 1;
}
/* enable interrupt as BIOS might not */
pci_write_config(dev, 0x71, 0x01, 1);
ctlr->ch_attach = ata_cmd_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->setmode = ata_cmd_setmode;
break;
}
return 0;
}
static int
ata_siiprb_begin_transaction(struct ata_request *request)
{
struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
struct ata_channel *ch = device_get_softc(request->parent);
struct ata_siiprb_command *prb;
struct ata_siiprb_dma_prdentry *prd;
int offset = ch->unit * 0x2000;
u_int64_t prb_bus;
/* SOS XXX */
if (request->u.ata.command == ATA_DEVICE_RESET) {
request->result = 0;
return ATA_OP_FINISHED;
}
/* get a piece of the workspace for this request */
prb = (struct ata_siiprb_command *)ch->dma.work;
/* clear the prb structure */
bzero(prb, sizeof(struct ata_siiprb_command));
/* setup the FIS for this request */
if (!ata_request2fis_h2d(request, &prb->fis[0])) {
device_printf(request->parent, "setting up SATA FIS failed\n");
request->result = EIO;
return ATA_OP_FINISHED;
}
/* setup transfer type */
if (request->flags & ATA_R_ATAPI) {
bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
if (request->flags & ATA_R_ATAPI16)
ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
else
ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
if (request->flags & ATA_R_READ)
prb->control = htole16(0x0010);
if (request->flags & ATA_R_WRITE)
prb->control = htole16(0x0020);
prd = &prb->u.atapi.prd[0];
}
else
prd = &prb->u.ata.prd[0];
/* if request moves data setup and load SG list */
if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
if (ch->dma.load(request, prd, NULL)) {
device_printf(request->parent, "setting up DMA failed\n");
request->result = EIO;
return ATA_OP_FINISHED;
}
}
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
/* activate the prb */
prb_bus = ch->dma.work_bus;
ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
/* start the timeout */
callout_reset(&request->callout, request->timeout * hz,
(timeout_t*)ata_timeout, request);
return ATA_OP_CONTINUES;
}
static int
ata_siiprb_end_transaction(struct ata_request *request)
{
struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
struct ata_channel *ch = device_get_softc(request->parent);
struct ata_siiprb_command *prb;
int offset = ch->unit * 0x2000;
int error, timeout;
/* kill the timeout */
callout_stop(&request->callout);
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
prb = (struct ata_siiprb_command *)
((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
/* any controller errors flagged ? */
if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
if (bootverbose)
printf("ata_siiprb_end_transaction %s error=%08x\n",
ata_cmd2str(request), error);
/* if device error status get details */
if (error == 1 || error == 2) {
request->status = prb->fis[2];
if (request->status & ATA_S_ERROR)
request->error = prb->fis[3];
}
/* SOS XXX handle other controller errors here */
/* initialize port */
ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
/* poll for port ready */
for (timeout = 0; timeout < 1000; timeout++) {
DELAY(1000);
if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
break;
}
if (bootverbose) {
if (timeout >= 1000)
device_printf(ch->dev, "port initialize timeout\n");
else
device_printf(ch->dev, "port initialize time=%dms\n", timeout);
}
}
/* on control commands read back registers to the request struct */
if (request->flags & ATA_R_CONTROL) {
request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
((u_int64_t)prb->fis[6] << 16);
if (request->flags & ATA_R_48BIT)
request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
((u_int64_t)prb->fis[9] << 32) |
((u_int64_t)prb->fis[10] << 40);
else
request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
}
/* update progress */
if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
if (request->flags & ATA_R_READ)
request->donecount = le32toh(prb->transfer_count);
else
request->donecount = request->bytecount;
}
/* release SG list etc */
ch->dma.unload(request);
return ATA_OP_FINISHED;
}
static void
ata_siiprb_reset(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int offset = ch->unit * 0x2000;
u_int32_t status, signature;
int timeout;
/* disable interrupts */
ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
/* reset channel HW */
ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
DELAY(1000);
ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
DELAY(10000);
/* poll for channel ready */
for (timeout = 0; timeout < 1000; timeout++) {
if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
break;
DELAY(1000);
}
if (bootverbose) {
if (timeout >= 1000)
device_printf(dev, "channel HW reset timeout\n");
else
device_printf(dev, "channel HW reset time=%dms\n", timeout);
}
/* reset phy */
if (!ata_sata_phy_reset(dev, -1, 1)) {
if (bootverbose)
device_printf(dev, "phy reset found no device\n");
ch->devices = 0;
goto finish;
}
/* issue soft reset */
signature = ata_siiprb_softreset(dev, ATA_PM);
if (bootverbose)
device_printf(dev, "SIGNATURE=%08x\n", signature);
/* figure out whats there */
switch (signature >> 16) {
case 0x0000:
ch->devices = ATA_ATA_MASTER;
break;
case 0x9669:
ch->devices = ATA_PORTMULTIPLIER;
ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
//SOS XXX need to clear all PM status and interrupts!!!!
ata_pm_identify(dev);
break;
case 0xeb14:
ch->devices = ATA_ATAPI_MASTER;
break;
default:
ch->devices = 0;
}
if (bootverbose)
device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
finish:
/* clear interrupt(s) */
ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
/* require explicit interrupt ack */
ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
/* 64bit mode */
ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
/* enable interrupts wanted */
ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
}
