static int
apb_filter(void *arg)
{
struct apb_softc *sc = arg;
struct intr_event *event;
uint32_t reg, irq;
if(ar531x_soc >= AR531X_SOC_AR5315)
reg = ATH_READ_REG(AR5315_SYSREG_BASE +
AR5315_SYSREG_MISC_INTSTAT);
else
reg = ATH_READ_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_MISC_INTSTAT);
for (irq = 0; irq < APB_NIRQS; irq++) {
if (reg & (1 << irq)) {
if(ar531x_soc >= AR531X_SOC_AR5315) {
ATH_WRITE_REG(AR5315_SYSREG_BASE +
AR5315_SYSREG_MISC_INTSTAT,
reg & ~(1 << irq));
} else {
ATH_WRITE_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_MISC_INTSTAT,
reg & ~(1 << irq));
}
event = sc->sc_eventstab[irq];
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
if(irq == 1 && ar531x_soc < AR531X_SOC_AR5315) {
ATH_READ_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_AHBPERR);
ATH_READ_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_AHBDMAE);
}
/* Ignore non handle interrupts */
if (irq != 0 && irq != 6)
printf("Stray APB IRQ %d\n", irq);
continue;
}
intr_event_handle(event, PCPU_GET(curthread)->td_intr_frame);
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
}
}
return (FILTER_HANDLED);
}
static int
apb_filter(void *arg)
{
struct apb_softc *sc = arg;
struct intr_event *event;
uint32_t reg, irq;
struct thread *td;
struct trapframe *tf;
reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS);
for (irq = 0; irq < APB_NIRQS; irq++) {
if (reg & (1 << irq)) {
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
case AR71XX_SOC_QCA9533:
case AR71XX_SOC_QCA9533_V2:
case AR71XX_SOC_QCA9556:
case AR71XX_SOC_QCA9558:
/* ACK/clear the given interrupt */
ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
(1 << irq));
break;
default:
/* fallthrough */
break;
}
event = sc->sc_eventstab[irq];
/* always count interrupts; spurious or otherwise */
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
if (irq == APB_INTR_PMC) {
td = PCPU_GET(curthread);
tf = td->td_intr_frame;
if (pmc_intr)
(*pmc_intr)(PCPU_GET(cpuid), tf);
continue;
}
/* Ignore timer interrupts */
if (irq != 0 && irq != 8 && irq != 9 && irq != 10)
printf("Stray APB IRQ %d\n", irq);
continue;
}
intr_event_handle(event, PCPU_GET(curthread)->td_intr_frame);
}
}
return (FILTER_HANDLED);
}
static void
apb_unmask_irq(void *source)
{
uint32_t reg;
unsigned int irq = (unsigned int)source;
reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK);
ATH_WRITE_REG(AR71XX_MISC_INTR_MASK, reg | (1 << irq));
}
static void
apb_mask_irq(void *source)
{
unsigned int irq = (unsigned int)source;
uint32_t reg;
if(ar531x_soc >= AR531X_SOC_AR5315) {
reg = ATH_READ_REG(AR5315_SYSREG_BASE +
AR5315_SYSREG_MISC_INTMASK);
ATH_WRITE_REG(AR5315_SYSREG_BASE
+ AR5315_SYSREG_MISC_INTMASK, reg & ~(1 << irq));
} else {
reg = ATH_READ_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_MISC_INTMASK);
ATH_WRITE_REG(AR5312_SYSREG_BASE
+ AR5312_SYSREG_MISC_INTMASK, reg & ~(1 << irq));
}
}
static void
apb_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
{
uint32_t reg, irq;
irq = ((struct apb_pic_irqsrc *)isrc)->irq;
if(ar531x_soc >= AR531X_SOC_AR5315) {
reg = ATH_READ_REG(AR5315_SYSREG_BASE +
AR5315_SYSREG_MISC_INTSTAT);
ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_MISC_INTSTAT,
reg & ~(1 << irq));
} else {
reg = ATH_READ_REG(AR5312_SYSREG_BASE +
AR5312_SYSREG_MISC_INTSTAT);
ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_MISC_INTSTAT,
reg & ~(1 << irq));
}
}
void
platform_reset(void)
{
uint32_t reg = ATH_READ_REG(AR71XX_RST_RESET);
ATH_WRITE_REG(AR71XX_RST_RESET, reg | RST_RESET_FULL_CHIP);
/* Wait for reset */
while(1)
;
}
static int
apb_intr(void *arg)
{
struct apb_softc *sc = arg;
struct intr_event *event;
uint32_t reg, irq;
reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS);
for (irq = 0; irq < APB_NIRQS; irq++) {
if (reg & (1 << irq)) {
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
/* Ack/clear the irq on status register for AR724x */
ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
reg & ~(1 << irq));
break;
default:
/* fallthrough */
break;
}
event = sc->sc_eventstab[irq];
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
/* Ignore timer interrupts */
if (irq != 0)
printf("Stray APB IRQ %d\n", irq);
continue;
}
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
}
}
return (FILTER_HANDLED);
}
void
platform_start(__register_t a0 __unused, __register_t a1 __unused,
__register_t a2 __unused, __register_t a3 __unused)
{
uint64_t platform_counter_freq;
uint32_t reg;
int argc, i, count = 0;
char **argv, **envp;
vm_offset_t kernend;
/*
* clear the BSS and SBSS segments, this should be first call in
* the function
*/
kernend = (vm_offset_t)&end;
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
mips_postboot_fixup();
/* Initialize pcpu stuff */
mips_pcpu0_init();
argc = a0;
argv = (char**)a1;
envp = (char**)a2;
/*
* Protect ourselves from garbage in registers
*/
if (MIPS_IS_VALID_PTR(envp)) {
for (i = 0; envp[i]; i += 2)
{
if (strcmp(envp[i], "memsize") == 0)
realmem = btoc(strtoul(envp[i+1], NULL, 16));
else if (strcmp(envp[i], "ethaddr") == 0) {
count = sscanf(envp[i+1], "%x.%x.%x.%x.%x.%x",
&ar711_base_mac[0], &ar711_base_mac[1],
&ar711_base_mac[2], &ar711_base_mac[3],
&ar711_base_mac[4], &ar711_base_mac[5]);
if (count < 6)
memset(ar711_base_mac, 0,
sizeof(ar711_base_mac));
}
}
}
/*
* Just wild guess. RedBoot let us down and didn't reported
* memory size
*/
if (realmem == 0)
realmem = btoc(32*1024*1024);
/* phys_avail regions are in bytes */
phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
phys_avail[1] = ctob(realmem);
physmem = realmem;
/*
* ns8250 uart code uses DELAY so ticker should be inititalized
* before cninit. And tick_init_params refers to hz, so * init_param1
* should be called first.
*/
init_param1();
platform_counter_freq = ar71xx_cpu_freq();
mips_timer_init_params(platform_counter_freq, 1);
cninit();
init_static_kenv(boot1_env, sizeof(boot1_env));
printf("platform frequency: %lld\n", platform_counter_freq);
printf("arguments: \n");
printf(" a0 = %08x\n", a0);
printf(" a1 = %08x\n", a1);
printf(" a2 = %08x\n", a2);
printf(" a3 = %08x\n", a3);
printf("Cmd line:");
if (MIPS_IS_VALID_PTR(argv)) {
for (i = 0; i < argc; i++) {
printf(" %s", argv[i]);
parse_argv(argv[i]);
}
}
else
printf ("argv is invalid");
printf("\n");
printf("Environment:\n");
if (MIPS_IS_VALID_PTR(envp)) {
for (i = 0; envp[i]; i+=2) {
printf(" %s = %s\n", envp[i], envp[i+1]);
setenv(envp[i], envp[i+1]);
}
}
else
printf ("envp is invalid\n");
init_param2(physmem);
mips_cpu_init();
pmap_bootstrap();
mips_proc0_init();
mutex_init();
/*
* Reset USB devices
*/
reg = ATH_READ_REG(AR71XX_RST_RESET);
reg |=
RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY;
ATH_WRITE_REG(AR71XX_RST_RESET, reg);
DELAY(1000);
reg &=
~(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
ATH_WRITE_REG(AR71XX_RST_RESET, reg);
ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
(32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
DELAY(1000);
kdb_init();
#ifdef KDB
if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif
}
static int
apb_attach(device_t dev)
{
struct apb_softc *sc = device_get_softc(dev);
#ifdef INTRNG
intptr_t xref = pic_xref(dev);
int miscirq;
#else
int rid = 0;
#endif
sc->apb_dev = dev;
sc->apb_mem_rman.rm_type = RMAN_ARRAY;
sc->apb_mem_rman.rm_descr = "APB memory window";
if(ar531x_soc >= AR531X_SOC_AR5315) {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5315_APB_BASE,
AR5315_APB_BASE + AR5315_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
} else {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5312_APB_BASE,
AR5312_APB_BASE + AR5312_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
}
sc->apb_irq_rman.rm_type = RMAN_ARRAY;
sc->apb_irq_rman.rm_descr = "APB IRQ";
if (rman_init(&sc->apb_irq_rman) != 0 ||
rman_manage_region(&sc->apb_irq_rman,
APB_IRQ_BASE, APB_IRQ_END) != 0)
panic("apb_attach: failed to set up IRQ rman");
#ifndef INTRNG
if ((sc->sc_misc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->sc_misc_irq, INTR_TYPE_MISC,
apb_filter, NULL, sc, &sc->sc_misc_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
#else
/* Register the interrupts */
if (apb_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
return (ENXIO);
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
return (ENXIO);
}
if(ar531x_soc >= AR531X_SOC_AR5315) {
miscirq = AR5315_CPU_IRQ_MISC;
} else {
miscirq = AR5312_IRQ_MISC;
}
cpu_establish_hardintr("aric", apb_filter, NULL, sc, miscirq,
INTR_TYPE_MISC, NULL);
#endif
/* mask all misc interrupt */
if(ar531x_soc >= AR531X_SOC_AR5315) {
ATH_WRITE_REG(AR5315_SYSREG_BASE
+ AR5315_SYSREG_MISC_INTMASK, 0);
} else {
ATH_WRITE_REG(AR5312_SYSREG_BASE
+ AR5312_SYSREG_MISC_INTMASK, 0);
}
bus_generic_probe(dev);
bus_enumerate_hinted_children(dev);
bus_generic_attach(dev);
return (0);
}
