int qdec_configure_interrupts(volatile avr32_qdec_t *qdec, const qdec_interrupt_t *bitfield)
{
AVR32_ENTER_CRITICAL_REGION( );
// Enable the appropriate interrupts.
qdec->ier = bitfield->ovr << AVR32_QDEC_IER_OVR_OFFSET |
bitfield->dirinv << AVR32_QDEC_IER_DIRINV_OFFSET |
bitfield->idexerr << AVR32_QDEC_IER_IDXERR_OFFSET |
bitfield->rcro << AVR32_QDEC_IER_RCRO_OFFSET |
bitfield->pcro << AVR32_QDEC_IER_PCRO_OFFSET |
bitfield->cap << AVR32_QDEC_IER_CAP_OFFSET |
bitfield->cmp << AVR32_QDEC_IER_CMP_OFFSET |
bitfield->qepi << AVR32_QDEC_IER_QEPI_OFFSET;
// Disable the appropriate interrupts.
qdec->idr = (~bitfield->ovr & 1) << AVR32_QDEC_IER_OVR_OFFSET |
(~bitfield->dirinv & 1) << AVR32_QDEC_IER_DIRINV_OFFSET |
(~bitfield->idexerr & 1) << AVR32_QDEC_IER_IDXERR_OFFSET |
(~bitfield->rcro & 1) << AVR32_QDEC_IER_RCRO_OFFSET |
(~bitfield->pcro & 1) << AVR32_QDEC_IER_PCRO_OFFSET |
(~bitfield->cap & 1) << AVR32_QDEC_IER_CAP_OFFSET |
(~bitfield->cmp & 1) << AVR32_QDEC_IER_CMP_OFFSET |
(~bitfield->qepi & 1) << AVR32_QDEC_IER_QEPI_OFFSET;
AVR32_LEAVE_CRITICAL_REGION( );
return 0;
}
long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
{
u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
#ifdef AVR32SFW_INPUT_CHECK
// Check that the input frequency is in the supported frequency range.
if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
|| (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
{
return -1;
}
// Check : for OSC0, only 2 modes are supported
if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
&& (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
{
return -1;
}
if (osc == SCIF_OSC0)
{
// Check that the startup value is in the supported range.
if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
{
return -1;
}
// Check that the gain value is in the supported range.
if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
{
return -1;
}
}
else
{
return -1;
}
#endif // AVR32SFW_INPUT_CHECK
// Read Register
u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
// Modify: Configure & start OSC0.
u_avr32_scif_oscctrl.OSCCTRL[osc].mode = opt->mode;
u_avr32_scif_oscctrl.OSCCTRL[osc].gain = opt->gain;
u_avr32_scif_oscctrl.OSCCTRL[osc].startup = opt->startup;
u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
// Write Back
AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
AVR32_LEAVE_CRITICAL_REGION( );
if(true == wait_for_ready)
{
// Wait until OSC0 is stable and ready to be used.
if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
return -1;
}
return PASS;
}
long pm_set_mclk_source(pm_clk_src_t src)
{
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected MCCTRL register
PM_UNLOCK(AVR32_PM_MCCTRL);
AVR32_PM.mcctrl = src;
AVR32_LEAVE_CRITICAL_REGION( );
return PASS;
}
/**
* start timer
*/
void Timer::start()
{
if (timerState == TIMER_STOP)
{
long long elapTime = 0;
unsigned int countReg = 0;
timerState = TIMER_START;
AVR32_ENTER_CRITICAL_REGION(); // disable interrupts
countReg = Get_sys_count();
Set_sys_compare(countReg + 10); // the next timer irq will occur before leaving this function
AVR32_LEAVE_CRITICAL_REGION(); // enable interrupts, if have been enabled before AVR32_ENTER_CRITICAL_REGION
elapTime = 1000000000/(CPU_CLK/1000000);
elapTime *= (countReg + 10);
elapTime /= 1000000;
nanoTime += elapTime;
}
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl0.OSCCTRL0.gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
// Write Back
AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 11;
break;
case 16000000:
mul = 5;
break;
case 12000000:
default:
mul = 7;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 1;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll0_setup((const scif_pll_opt_t *)&opt);
/* Enable PLL0 */
scif_pll0_enable();
/* Wait for PLL0 locked */
scif_wait_for_pll0_locked();
// Configure and start the RC120Mhz internal oscillator.
scif_start_rc120M();
// Since our target is to set the CPU&HSB frequency domains to 30MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(30000000UL);
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
typedef union
{
unsigned long oscctrl[2];
avr32_scif_oscctrl_t OSCCTRL[2];
} u_avr32_scif_oscctrl_t;
u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
// Read Register
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
// Write Back
AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
flashc_set_flash_waitstate_and_readmode(16000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashc_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fPBA: 48 MHz
// fHSB: 48 MHz
// fPBB: 48 MHz must be the same that CPU
// fPBC: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_4); // PBC
// Use 0 flash wait state
flashc_set_wait_state(1);
}