/**
* FchInitEnvAbLinkInit - Set ABCFG registers before PCI
* emulation.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAbLinkInit (
IN VOID *FchDataPtr
)
{
UINT16 AbTempVar;
UINT8 AbValue8;
AB_TBL_ENTRY *AbTblPtr;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set A-Link bridge access address.
// This is an I/O address. The I/O address must be on 16-byte boundary.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX);
//
// AB CFG programming
//
if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, 0);
}
//
// Read Arbiter address, Arbiter address is in PMIO 6Ch
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar);
/// Write 0 to enable the arbiter
AbValue8 = 0;
LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
AbTblPtr = (AB_TBL_ENTRY *) (&KernInitEnvAbTable[0]);
AbCfgTbl (AbTblPtr, StdHeader);
//
// Need to check
//
if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) {
RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~(UINT32) BIT2, BIT2, StdHeader);
}
if ( LocalCfgPtr->Ab.AbDmaMemoryWrtie3264B ) {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader);
}
//
// A Clock Gate-OFF
//
if ( LocalCfgPtr->Ab.ALinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, BIT16);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0);
}
//
// B Clock Gate-OFF
//
if ( LocalCfgPtr->Ab.BLinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, BIT16);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0);
}
if ((LocalCfgPtr->Ab.ALinkClkGateOff == 0) && (LocalCfgPtr->Ab.BLinkClkGateOff == 0)) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, 0);
}
//
// GPP and GFX Clock Request
// remove to enable pci-e device
// RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00, AccessWidth8, 0xF0, LocalCfgPtr->Ab.GppClockRequest0);
// RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GppClockRequest1);
// RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00 + 1, AccessWidth8, 0xF0, LocalCfgPtr->Ab.GppClockRequest2);
// RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00 + 1, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GppClockRequest3);
// RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GfxClockRequest);
//
// AB Clock Gating
//
if ( LocalCfgPtr->Ab.AbClockGating ) {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), (UINT32) (0x3 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), 0, StdHeader);
}
//
// AB Memory Power Saving
//
if ( LocalCfgPtr->Ab.AbMemoryPowerSaving ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x00);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 29), (UINT32) (0x1 << 29), StdHeader);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 31), (UINT32) (0x1 << 31), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x5 << 29), (UINT32) 0x0, StdHeader);
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x04);
}
//
// SBG Memory Power Saving
//
if ( LocalCfgPtr->Ab.SbgMemoryPowerSaving ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFD, 0x00);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 7), (UINT32) (0x1 << 7), StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 9), (UINT32) (0x1 << 9), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 7), (UINT32) 0x0, StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 9), (UINT32) 0x0, StdHeader);
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFD, 0x02);
}
//
// SBG Clock Gating
//
if ( LocalCfgPtr->Ab.SbgClockGating ) {
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 22), (UINT32) (0x1 << 22), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x0), StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x0), StdHeader);
RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 22), (UINT32) (0x0), StdHeader);
}
//
// XDMA DMA Write 16 byte Mode
//
if ( LocalCfgPtr->Ab.XdmaDmaWrite16ByteMode ) {
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0), StdHeader);
}
//
// XDMA Memory Power Saving
//
if ( LocalCfgPtr->Ab.XdmaMemoryPowerSaving ) {
RwAlink (FCH_ABCFG_REG184 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG184 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader);
}
//
// XDMA Pending NPR Threshold
//
if ( LocalCfgPtr->Ab.XdmaPendingNprThreshold ) {
AbValue8 = LocalCfgPtr->Ab.XdmaPendingNprThreshold;
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x03 << 2), (UINT32) (AbValue8 << 2), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x03 << 2), (UINT32) (0x0), StdHeader);
}
//
// XDMA DNCPL Order Dis
//
if ( LocalCfgPtr->Ab.XdmaDncplOrderDis ) {
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 5), (UINT32) (0x1 << 5), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 5), (UINT32) (0x0), StdHeader);
}
}
/**
* FchInitEnvAbLinkInit - Set ABCFG registers before PCI
* emulation.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAbLinkInit (
IN VOID *FchDataPtr
)
{
UINT16 AbTempVar;
UINT8 AbValue8;
UINT8 FchALinkClkGateOff;
UINT8 FchBLinkClkGateOff;
AB_TBL_ENTRY *AbTblPtr;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff;
FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff;
//
// AB CFG programming
//
if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, 0);
}
//
// Read Arbiter address, Arbiter address is in PMIO 6Ch
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar);
/// Write 0 to enable the arbiter
AbValue8 = 0;
LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) {
AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]);
AbCfgTbl (AbTblPtr, StdHeader);
}
if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) {
RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader);
RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader);
}
AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]);
AbCfgTbl (AbTblPtr, StdHeader);
if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) {
RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~(UINT32) BIT2, BIT2, StdHeader);
}
if ( LocalCfgPtr->Ab.AbClockGating ) {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
}
if ( LocalCfgPtr->Ab.GppClockGating ) {
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader);
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
}
if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) {
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader);
}
if ( LocalCfgPtr->Ab.UmiLinkWidth ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) {
RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader);
RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader);
}
if ( LocalCfgPtr->Gpp.PcieAer ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Gpp.PcieRas ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
//
// Ab Bridge MSI
//
if ( LocalCfgPtr->Ab.AbMsiEnable) {
// AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader);
// AbValue = AbValue | BIT20;
// WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
}
//
// A/B Clock Gate-OFF
//
if ( FchALinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0x00);
}
if ( FchBLinkClkGateOff ) {
//RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0x00);
}
if ( FchALinkClkGateOff | FchBLinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, 0);
}
if ( ReadFchChipsetRevision ( StdHeader ) == FCH_BOLTON ) {
// Enable fix for race problem between PLL calibrator and LC wake up from L1.
RwAlink (FCH_AX_INDXC_REG02, ~(UINT32) (BIT8), BIT8, StdHeader);
// Set this bit to 1 to allow for proper ASPM L1 and L0s transitions when PLL power-down in L1 is enabled.
RwAlink ((FCH_ABCFG_REGB8 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, BIT30, StdHeader);
// A/B Clock Gate-OFF
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFC, 0x03);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0);
}
}
/**
* FchInitEnvAbLinkInit - Set ABCFG registers before PCI
* emulation.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAbLinkInit (
IN VOID *FchDataPtr
)
{
UINT16 AbTempVar;
UINT8 AbValue8;
AB_TBL_ENTRY *AbTblPtr;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// AB CFG programming
//
if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, 0);
}
//
// Read Arbiter address, Arbiter address is in PMIO 6Ch
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar);
/// Write 0 to enable the arbiter
AbValue8 = 0;
LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
AbTblPtr = (AB_TBL_ENTRY *) (&YangtzeInitEnvAbTable[0]);
AbCfgTbl (AbTblPtr, StdHeader);
if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) {
RwAlink (0x10050ul | (UINT32) (ABCFG << 29), (UINT32)~BIT2, BIT2, StdHeader);
}
if ( LocalCfgPtr->Ab.AbClockGating ) {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), (UINT32) (0x3 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), 0, StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), 0, StdHeader);
}
if ( LocalCfgPtr->Ab.AbDmaMemoryWrtie3264B ) {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader);
}
if ( LocalCfgPtr->Ab.AbMemoryPowerSaving ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x00);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 29), (UINT32) (0x1 << 29), StdHeader);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 31), (UINT32) (0x1 << 31), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x5 << 29), (UINT32) 0x0, StdHeader);
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x04);
}
//
// A/B Clock Gate-OFF
//
if ( LocalCfgPtr->Ab.ALinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0);
}
if ( LocalCfgPtr->Ab.BLinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0);
}
if ( LocalCfgPtr->Ab.ALinkClkGateOff | LocalCfgPtr->Ab.BLinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, 0);
}
}
