/**Function*************************************************************
Synopsis [Create a constant 0 node driving the net with this name.]
Description [Assumes that the net already exists.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 )
{
Abc_Obj_t * pNet, * pTerm;
pTerm = fConst1? Abc_NtkCreateNodeConst1(pNtk) : Abc_NtkCreateNodeConst0(pNtk);
pNet = Abc_NtkFindNet(pNtk, pName); assert( pNet );
Abc_ObjAddFanin( pNet, pTerm );
return pTerm;
}
/**Function*************************************************************
Synopsis [Create node and the net driven by it.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut, char * pNamesIn[], int nInputs )
{
Abc_Obj_t * pNet, * pNode;
int i;
// create a new node
pNode = Abc_NtkCreateNode( pNtk );
// add the fanin nets
for ( i = 0; i < nInputs; i++ )
{
pNet = Abc_NtkFindOrCreateNet( pNtk, pNamesIn[i] );
Abc_ObjAddFanin( pNode, pNet );
}
// add the fanout net
pNet = Abc_NtkFindOrCreateNet( pNtk, pNameOut );
Abc_ObjAddFanin( pNet, pNode );
return pNode;
}
// create the missing nets
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( pObj->pCopy->pCopy ) // the net of the new object is already created
continue;
// create the new net
pNet = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pObj) ); // here we create ridiculous names net line "n48", where 48 is the ID of the node
Abc_ObjAddFanin( pNet, pObj->pCopy );
pObj->pCopy->pCopy = pNet;
}
/**Function*************************************************************
Synopsis [Create an inverter or buffer for the given net.]
Description [Assumes that the nets already exist.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut )
{
Abc_Obj_t * pNet, * pNode;
pNet = Abc_NtkFindNet(pNtk, pNameIn); assert( pNet );
pNode = Abc_NtkCreateNodeBuf(pNtk, pNet);
pNet = Abc_NtkFindNet(pNtk, pNameOut); assert( pNet );
Abc_ObjAddFanin( pNet, pNode );
return pNet;
}
/**Function*************************************************************
Synopsis [Finalizes the network using the existing network as a model.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkFinalize( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
Abc_Obj_t * pObj, * pDriver, * pDriverNew;
int i;
// set the COs of the strashed network
Abc_NtkForEachCo( pNtk, pObj, i )
{
pDriver = Abc_ObjFanin0Ntk( Abc_ObjFanin0(pObj) );
pDriverNew = Abc_ObjNotCond(pDriver->pCopy, Abc_ObjFaninC0(pObj));
Abc_ObjAddFanin( pObj->pCopy, pDriverNew );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Implements the function.]
Description [Returns the node implementing this function.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Lpk_ImplementFun( Lpk_Man_t * pMan, Abc_Ntk_t * pNtk, Vec_Ptr_t * vLeaves, Lpk_Fun_t * p )
{
extern Hop_Obj_t * Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
unsigned * pTruth;
Abc_Obj_t * pObjNew;
int i;
if ( p->fMark )
pMan->nMuxes++;
else
pMan->nDsds++;
// create the new node
pObjNew = Abc_NtkCreateNode( pNtk );
for ( i = 0; i < (int)p->nVars; i++ )
Abc_ObjAddFanin( pObjNew, Abc_ObjRegular((Abc_Obj_t *)Vec_PtrEntry(vLeaves, p->pFanins[i])) );
Abc_ObjSetLevel( pObjNew, Abc_ObjLevelNew(pObjNew) );
// assign the node's function
pTruth = Lpk_FunTruth(p, 0);
if ( p->nVars == 0 )
{
pObjNew->pData = Hop_NotCond( Hop_ManConst1((Hop_Man_t *)pNtk->pManFunc), !(pTruth[0] & 1) );
return pObjNew;
}
if ( p->nVars == 1 )
{
pObjNew->pData = Hop_NotCond( Hop_ManPi((Hop_Man_t *)pNtk->pManFunc, 0), (pTruth[0] & 1) );
return pObjNew;
}
// create the logic function
pObjNew->pData = Kit_TruthToHop( (Hop_Man_t *)pNtk->pManFunc, pTruth, p->nVars, NULL );
return pObjNew;
}
/**Function*************************************************************
Synopsis [Create a latch with the given input/output.]
Description [By default, the latch value is unknown (ABC_INIT_NONE).]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
{
Abc_Obj_t * pLatch, * pTerm, * pNet;
// get the LI net
pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI );
// add the BO terminal
pTerm = Abc_NtkCreateBi( pNtk );
Abc_ObjAddFanin( pTerm, pNet );
// add the latch box
pLatch = Abc_NtkCreateLatch( pNtk );
Abc_ObjAddFanin( pLatch, pTerm );
// add the BI terminal
pTerm = Abc_NtkCreateBo( pNtk );
Abc_ObjAddFanin( pTerm, pLatch );
// get the LO net
pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO );
Abc_ObjAddFanin( pNet, pTerm );
// set latch name
Abc_ObjAssignName( pLatch, pNetLO, "L" );
return pLatch;
}
// create the fanouts of the box
Abc_NtkForEachPo( pNtkModel, pObj, i )
{
pActual = (char *)pObj->pCopy;
if ( pActual == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Formal output \"%s\" of model %s is not driven.", pName, (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
pNet = Abc_NtkFindOrCreateNet( pBox->pNtk, pActual );
Abc_ObjAddFanin( pNet, pBox );
}
/**Function*************************************************************
Synopsis [Creates PO terminal and net.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName )
{
Abc_Obj_t * pNet, * pTerm;
// get the PO net
pNet = Abc_NtkFindNet( pNtk, pName );
if ( pNet && Abc_ObjFaninNum(pNet) == 0 )
printf( "Warning: Assert \"%s\" appears twice in the list.\n", pName );
pNet = Abc_NtkFindOrCreateNet( pNtk, pName );
// add the PO node
pTerm = Abc_NtkCreateAssert( pNtk );
Abc_ObjAddFanin( pTerm, pNet );
return pTerm;
}
/**Function*************************************************************
Synopsis [Creates PI terminal and net.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName )
{
Abc_Obj_t * pNet, * pTerm;
// get the PI net
pNet = Abc_NtkFindNet( pNtk, pName );
if ( pNet )
printf( "Warning: PI \"%s\" appears twice in the list.\n", pName );
pNet = Abc_NtkFindOrCreateNet( pNtk, pName );
// add the PI node
pTerm = Abc_NtkCreatePi( pNtk );
Abc_ObjAddFanin( pNet, pTerm );
return pTerm;
}
Abc_NtkForEachObj( pNtk, pObj, i )
{
// skip constants, PIs, and latches
if ( Abc_ObjFaninNum(pObj) == 0 || Abc_ObjIsLatch(pObj) )
continue;
// process the first fanin
Vec_IntClear( vInitValues );
pFaninNew = Abc_NodeAigToSeq( pObj->pCopy, pObj, 0, vInitValues );
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
// store the initial values
Vec_IntForEachEntry( vInitValues, Init, k )
Seq_NodeInsertFirst( pObj->pCopy, 0, Init );
// skip single-input nodes
if ( Abc_ObjFaninNum(pObj) == 1 )
continue;
// process the second fanin
Vec_IntClear( vInitValues );
pFaninNew = Abc_NodeAigToSeq( pObj->pCopy, pObj, 1, vInitValues );
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
// store the initial values
Vec_IntForEachEntry( vInitValues, Init, k )
Seq_NodeInsertFirst( pObj->pCopy, 1, Init );
}
/**Function*************************************************************
Synopsis [Creates the mapped network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeFromMapSuper_rec( Abc_Ntk_t * pNtkNew, Map_Node_t * pNodeMap, Map_Super_t * pSuper, Abc_Obj_t * pNodePis[], int nNodePis )
{
Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen();
Mio_Gate_t * pRoot;
Map_Super_t ** ppFanins;
Abc_Obj_t * pNodeNew, * pNodeFanin;
int nFanins, Number, i;
// get the parameters of the supergate
pRoot = Map_SuperReadRoot(pSuper);
if ( pRoot == NULL )
{
Number = Map_SuperReadNum(pSuper);
if ( Number < nNodePis )
{
return pNodePis[Number];
}
else
{
// assert( 0 );
/* It might happen that a super gate with 5 inputs is constructed that
* actually depends only on the first four variables; i.e the fifth is a
* don't care -- in that case we connect constant node for the fifth
* (since the cut only has 4 variables). An interesting question is what
* if the first variable (and not the fifth one is the redundant one;
* can that happen?) */
return Abc_NtkCreateNodeConst0(pNtkNew);
}
}
pRoot = Mio_LibraryReadGateByName( pLib, Mio_GateReadName(pRoot), NULL );
// get information about the fanins of the supergate
nFanins = Map_SuperReadFaninNum( pSuper );
ppFanins = Map_SuperReadFanins( pSuper );
// create a new node with these fanins
pNodeNew = Abc_NtkCreateNode( pNtkNew );
for ( i = 0; i < nFanins; i++ )
{
pNodeFanin = Abc_NodeFromMapSuper_rec( pNtkNew, pNodeMap, ppFanins[i], pNodePis, nNodePis );
Abc_ObjAddFanin( pNodeNew, pNodeFanin );
}
pNodeNew->pData = pRoot;
return pNodeNew;
}
Abc_Ntk_t * Abc_NtkFromMiniAig( Mini_Aig_t * p )
{
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObj;
Vec_Int_t * vCopies;
int i, nNodes;
// get the number of nodes
nNodes = Mini_AigNodeNum(p);
// create ABC network
pNtk = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
pNtk->pName = Abc_UtilStrsav( "MiniAig" );
// create mapping from MiniAIG objects into ABC objects
vCopies = Vec_IntAlloc( nNodes );
Vec_IntPush( vCopies, Abc_LitNot(Abc_ObjToLit(Abc_AigConst1(pNtk))) );
// iterate through the objects
for ( i = 1; i < nNodes; i++ )
{
if ( Mini_AigNodeIsPi( p, i ) )
pObj = Abc_NtkCreatePi(pNtk);
else if ( Mini_AigNodeIsPo( p, i ) )
Abc_ObjAddFanin( (pObj = Abc_NtkCreatePo(pNtk)), Abc_NodeFanin0Copy(pNtk, vCopies, p, i) );
else if ( Mini_AigNodeIsAnd( p, i ) )
pObj = Abc_AigAnd((Abc_Aig_t *)pNtk->pManFunc, Abc_NodeFanin0Copy(pNtk, vCopies, p, i), Abc_NodeFanin1Copy(pNtk, vCopies, p, i));
else assert( 0 );
Vec_IntPush( vCopies, Abc_ObjToLit(pObj) );
}
assert( Vec_IntSize(vCopies) == nNodes );
Abc_AigCleanup( (Abc_Aig_t *)pNtk->pManFunc );
Vec_IntFree( vCopies );
Abc_NtkAddDummyPiNames( pNtk );
Abc_NtkAddDummyPoNames( pNtk );
if ( !Abc_NtkCheck( pNtk ) )
fprintf( stdout, "Abc_NtkFromMini(): Network check has failed.\n" );
// add latches
if ( Mini_AigRegNum(p) > 0 )
{
extern Abc_Ntk_t * Abc_NtkRestrashWithLatches( Abc_Ntk_t * pNtk, int nLatches );
Abc_Ntk_t * pTemp;
pNtk = Abc_NtkRestrashWithLatches( pTemp = pNtk, Mini_AigRegNum(p) );
Abc_NtkDelete( pTemp );
}
return pNtk;
}
/**Function*************************************************************
Synopsis [Transforms the node to take fanout sharing into account.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Seq_NodeShareOne( Abc_Obj_t * pNode, Abc_InitType_t Init, Vec_Ptr_t * vNodes )
{
Vec_Int_t * vNums = Seq_ObjLNums( pNode );
Vec_Ptr_t * vInits = Seq_NodeLats( pNode );
Abc_Obj_t * pFanout, * pBuffer;
Abc_InitType_t Type, InitNew;
int i;
// collect the fanouts that satisfy the property (have initial value Init or DC)
InitNew = ABC_INIT_DC;
Vec_PtrClear( vNodes );
Abc_ObjForEachFanout( pNode, pFanout, i )
{
if ( Seq_ObjFanoutL(pNode, pFanout) == 0 )
continue;
Type = Seq_NodeGetInitLast( pFanout, Abc_ObjFanoutEdgeNum(pNode, pFanout) );
if ( Type == Init )
InitNew = Init;
if ( Type == Init || Type == ABC_INIT_DC )
{
Vec_PtrPush( vNodes, pFanout );
Seq_NodeDeleteLast( pFanout, Abc_ObjFanoutEdgeNum(pNode, pFanout) );
}
}
// create the new buffer
pBuffer = Abc_NtkCreateNode( pNode->pNtk );
Abc_ObjAddFanin( pBuffer, pNode );
// grow storage for initial states
Vec_PtrGrow( vInits, 2 * pBuffer->Id + 2 );
for ( i = Vec_PtrSize(vInits); i < 2 * (int)pBuffer->Id + 2; i++ )
Vec_PtrPush( vInits, NULL );
// grow storage for numbers of latches
Vec_IntGrow( vNums, 2 * pBuffer->Id + 2 );
for ( i = Vec_IntSize(vNums); i < 2 * (int)pBuffer->Id + 2; i++ )
Vec_IntPush( vNums, 0 );
// insert the new latch
Seq_NodeInsertFirst( pBuffer, 0, InitNew );
// redirect the fanouts
Vec_PtrForEachEntry( vNodes, pFanout, i )
Abc_ObjPatchFanin( pFanout, pNode, pBuffer );
}
/**Function*************************************************************
Synopsis [Create the reset latch with data=1 and init=0.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Io_ReadCreateResetLatch( Abc_Ntk_t * pNtk, int fBlifMv )
{
Abc_Obj_t * pLatch, * pNode;
Abc_Obj_t * pNetLI, * pNetLO;
// create latch with 0 init value
// pLatch = Io_ReadCreateLatch( pNtk, "_resetLI_", "_resetLO_" );
pNetLI = Abc_NtkCreateNet( pNtk );
pNetLO = Abc_NtkCreateNet( pNtk );
Abc_ObjAssignName( pNetLI, Abc_ObjName(pNetLI), NULL );
Abc_ObjAssignName( pNetLO, Abc_ObjName(pNetLO), NULL );
pLatch = Io_ReadCreateLatch( pNtk, Abc_ObjName(pNetLI), Abc_ObjName(pNetLO) );
// set the initial value
Abc_LatchSetInit0( pLatch );
// feed the latch with constant1- node
// pNode = Abc_NtkCreateNode( pNtk );
// pNode->pData = Abc_SopRegister( pNtk->pManFunc, "2\n1\n" );
pNode = Abc_NtkCreateNodeConst1( pNtk );
Abc_ObjAddFanin( Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pNode );
return pLatch;
}
/**Function*************************************************************
Synopsis [Constructs the ABC network after mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Ivy_ManFpgaToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObjAbc, * pObj;
Ivy_Obj_t * pObjIvy;
Vec_Int_t * vNodes;
int i;
// start mapping from Ivy into Abc
pMan->pCopy = Vec_PtrStart( Ivy_ManObjIdMax(pMan) + 1 );
// start the new ABC network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_AIG );
// transfer the pointers to the basic nodes
Abc_ObjSetIvy2Abc( pMan, Ivy_ManConst1(pMan)->Id, Abc_NtkCreateNodeConst1(pNtkNew) );
Abc_NtkForEachCi( pNtkNew, pObjAbc, i )
Abc_ObjSetIvy2Abc( pMan, Ivy_ManPi(pMan, i)->Id, pObjAbc );
// recursively construct the network
vNodes = Vec_IntAlloc( 100 );
Ivy_ManForEachPo( pMan, pObjIvy, i )
{
// get the new ABC node corresponding to the old fanin of the PO in IVY
pObjAbc = Ivy_ManToAbcFast_rec( pNtkNew, pMan, Ivy_ObjFanin0(pObjIvy), vNodes );
// consider the case of complemented fanin of the PO
if ( Ivy_ObjFaninC0(pObjIvy) ) // complement
{
if ( Abc_ObjIsCi(pObjAbc) )
pObjAbc = Abc_NtkCreateNodeInv( pNtkNew, pObjAbc );
else
{
// clone the node
pObj = Abc_NtkCloneObj( pObjAbc );
// set complemented functions
pObj->pData = Hop_Not( pObjAbc->pData );
// return the new node
pObjAbc = pObj;
}
}
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjAbc );
}
/**Function*************************************************************
Synopsis [Converts the network from the AIG manager into ABC.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFromMini( Abc_Ntk_t * pNtk, Hop_Man_t * pMan )
{
Vec_Ptr_t * vNodes;
Abc_Ntk_t * pNtkNew;
Hop_Obj_t * pObj;
int i;
// perform strashing
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
// transfer the pointers to the basic nodes
Hop_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
Hop_ManForEachPi( pMan, pObj, i )
pObj->pData = Abc_NtkCi(pNtkNew, i);
// rebuild the AIG
vNodes = Hop_ManDfs( pMan );
Vec_PtrForEachEntry( Hop_Obj_t *, vNodes, pObj, i )
pObj->pData = Abc_AigAnd( (Abc_Aig_t *)pNtkNew->pManFunc, (Abc_Obj_t *)Hop_ObjChild0Copy(pObj), (Abc_Obj_t *)Hop_ObjChild1Copy(pObj) );
Vec_PtrFree( vNodes );
// connect the PO nodes
Hop_ManForEachPo( pMan, pObj, i )
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Hop_ObjChild0Copy(pObj) );
if ( !Abc_NtkCheck( pNtkNew ) )
fprintf( stdout, "Abc_NtkFromMini(): Network check has failed.\n" );
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Connect one box.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Io_ReadBlifNetworkConnectBoxesOneBox( Io_ReadBlif_t * p, Abc_Obj_t * pBox, stmm_table * tName2Model )
{
Vec_Ptr_t * pNames;
Abc_Ntk_t * pNtkModel;
Abc_Obj_t * pObj, * pNet;
char * pName = NULL, * pActual;
int i, Length, Start = -1;
// get the model for this box
pNames = (Vec_Ptr_t *)pBox->pData;
if ( !stmm_lookup( tName2Model, (char *)Vec_PtrEntry(pNames, 0), (char **)&pNtkModel ) )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot find the model for subcircuit %s.", (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
// create the fanins of the box
Abc_NtkForEachPi( pNtkModel, pObj, i )
pObj->pCopy = NULL;
if ( Abc_NtkPiNum(pNtkModel) == 0 )
Start = 1;
else
{
Vec_PtrForEachEntryStart( char *, pNames, pName, i, 1 )
{
pActual = Io_ReadBlifCleanName(pName);
if ( pActual == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot parse formal/actual name pair \"%s\".", pName );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
Length = pActual - pName - 1;
pName[Length] = 0;
// find the PI net with this name
pObj = Abc_NtkFindNet( pNtkModel, pName );
if ( pObj == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot find formal input \"%s\" as an PI of model \"%s\".", pName, (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
// get the PI
pObj = Abc_ObjFanin0(pObj);
// quit if this is not a PI net
if ( !Abc_ObjIsPi(pObj) )
{
pName[Length] = '=';
Start = i;
break;
}
// remember the actual name in the net
if ( pObj->pCopy != NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Formal input \"%s\" is used more than once.", pName );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
pObj->pCopy = (Abc_Obj_t *)pActual;
// quit if we processed all PIs
if ( i == Abc_NtkPiNum(pNtkModel) )
{
Start = i+1;
break;
}
}
}
// create the fanins of the box
Abc_NtkForEachPi( pNtkModel, pObj, i )
{
pActual = (char *)pObj->pCopy;
if ( pActual == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Formal input \"%s\" of model %s is not driven.", pName, (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
pNet = Abc_NtkFindOrCreateNet( pBox->pNtk, pActual );
Abc_ObjAddFanin( pBox, pNet );
}
/**Function*************************************************************
Synopsis [Adds a gate to the circuit.]
Description [The meaning of the parameters are:
type: the type of the gate to be added
name: the name of the gate to be added, name should be unique in a circuit.
nofi: number of fanins of the gate to be added;
fanins: the name array of fanins of the gate to be added.]
SideEffects []
SeeAlso []
***********************************************************************/
int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, char ** fanins, int dc_attr )
{
Abc_Obj_t * pObj = NULL; // Suppress "might be used uninitialized"
Abc_Obj_t * pFanin;
char * pSop = NULL; // Suppress "might be used uninitialized"
char * pNewName;
int i;
// save the name in the local memory manager
pNewName = Mem_FlexEntryFetch( mng->pMmNames, strlen(name) + 1 );
strcpy( pNewName, name );
name = pNewName;
// consider different cases, create the node, and map the node into the name
switch( type )
{
case CSAT_BPI:
case CSAT_BPPI:
if ( nofi != 0 )
{ printf( "ABC_AddGate: The PI/PPI gate \"%s\" has fanins.\n", name ); return 0; }
// create the PI
pObj = Abc_NtkCreatePi( mng->pNtk );
stmm_insert( mng->tNode2Name, (char *)pObj, name );
break;
case CSAT_CONST:
case CSAT_BAND:
case CSAT_BNAND:
case CSAT_BOR:
case CSAT_BNOR:
case CSAT_BXOR:
case CSAT_BXNOR:
case CSAT_BINV:
case CSAT_BBUF:
// create the node
pObj = Abc_NtkCreateNode( mng->pNtk );
// create the fanins
for ( i = 0; i < nofi; i++ )
{
if ( !stmm_lookup( mng->tName2Node, fanins[i], (char **)&pFanin ) )
{ printf( "ABC_AddGate: The fanin gate \"%s\" is not in the network.\n", fanins[i] ); return 0; }
Abc_ObjAddFanin( pObj, pFanin );
}
// create the node function
switch( type )
{
case CSAT_CONST:
if ( nofi != 0 )
{ printf( "ABC_AddGate: The constant gate \"%s\" has fanins.\n", name ); return 0; }
pSop = Abc_SopCreateConst1( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
case CSAT_BAND:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The AND gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateAnd( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi, NULL );
break;
case CSAT_BNAND:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The NAND gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNand( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The OR gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateOr( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi, NULL );
break;
case CSAT_BNOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The NOR gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BXOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The XOR gate \"%s\" no fanins.\n", name ); return 0; }
if ( nofi > 2 )
{ printf( "ABC_AddGate: The XOR gate \"%s\" has more than two fanins.\n", name ); return 0; }
pSop = Abc_SopCreateXor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BXNOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The XNOR gate \"%s\" no fanins.\n", name ); return 0; }
if ( nofi > 2 )
{ printf( "ABC_AddGate: The XNOR gate \"%s\" has more than two fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNxor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BINV:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The inverter gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
pSop = Abc_SopCreateInv( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
case CSAT_BBUF:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The buffer gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
pSop = Abc_SopCreateBuf( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
default :
break;
}
Abc_ObjSetData( pObj, pSop );
break;
case CSAT_BPPO:
case CSAT_BPO:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The PO/PPO gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
// create the PO
pObj = Abc_NtkCreatePo( mng->pNtk );
stmm_insert( mng->tNode2Name, (char *)pObj, name );
// connect to the PO fanin
if ( !stmm_lookup( mng->tName2Node, fanins[0], (char **)&pFanin ) )
{ printf( "ABC_AddGate: The fanin gate \"%s\" is not in the network.\n", fanins[0] ); return 0; }
Abc_ObjAddFanin( pObj, pFanin );
break;
default:
printf( "ABC_AddGate: Unknown gate type.\n" );
break;
}
// map the name into the node
if ( stmm_insert( mng->tName2Node, name, (char *)pObj ) )
{ printf( "ABC_AddGate: The same gate \"%s\" is added twice.\n", name ); return 0; }
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p )
{
ProgressBar * pProgress;
Vec_Ptr_t * vTokens;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pTermPi, * pTermPo, * pNode;
Vec_Str_t ** ppSops;
char Buffer[100];
int nInputs = -1, nOutputs = -1, nProducts = -1;
char * pCubeIn, * pCubeOut;
int i, k, iLine, nDigits, nCubes;
// allocate the empty network
pNtk = Abc_NtkStartRead( Extra_FileReaderGetFileName(p) );
// go through the lines of the file
nCubes = 0;
pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p) );
for ( iLine = 0; vTokens = Extra_FileReaderGetTokens(p); iLine++ )
{
Extra_ProgressBarUpdate( pProgress, Extra_FileReaderGetCurPosition(p), NULL );
// if it is the end of file, quit the loop
if ( strcmp( vTokens->pArray[0], ".e" ) == 0 )
break;
if ( vTokens->nSize == 1 )
{
printf( "%s (line %d): Wrong number of token.\n",
Extra_FileReaderGetFileName(p), iLine+1 );
Abc_NtkDelete( pNtk );
return NULL;
}
if ( strcmp( vTokens->pArray[0], ".i" ) == 0 )
nInputs = atoi(vTokens->pArray[1]);
else if ( strcmp( vTokens->pArray[0], ".o" ) == 0 )
nOutputs = atoi(vTokens->pArray[1]);
else if ( strcmp( vTokens->pArray[0], ".p" ) == 0 )
nProducts = atoi(vTokens->pArray[1]);
else if ( strcmp( vTokens->pArray[0], ".ilb" ) == 0 )
{
if ( vTokens->nSize - 1 != nInputs )
printf( "Warning: Mismatch between the number of PIs on the .i line (%d) and the number of PIs on the .ilb line (%d).\n", nInputs, vTokens->nSize - 1 );
for ( i = 1; i < vTokens->nSize; i++ )
Io_ReadCreatePi( pNtk, vTokens->pArray[i] );
}
else if ( strcmp( vTokens->pArray[0], ".ob" ) == 0 )
{
if ( vTokens->nSize - 1 != nOutputs )
printf( "Warning: Mismatch between the number of POs on the .o line (%d) and the number of POs on the .ob line (%d).\n", nOutputs, vTokens->nSize - 1 );
for ( i = 1; i < vTokens->nSize; i++ )
Io_ReadCreatePo( pNtk, vTokens->pArray[i] );
}
else
{
// check if the input/output names are given
if ( Abc_NtkPiNum(pNtk) == 0 )
{
if ( nInputs == -1 )
{
printf( "%s: The number of inputs is not specified.\n", Extra_FileReaderGetFileName(p) );
Abc_NtkDelete( pNtk );
return NULL;
}
nDigits = Extra_Base10Log( nInputs );
for ( i = 0; i < nInputs; i++ )
{
sprintf( Buffer, "x%0*d", nDigits, i );
Io_ReadCreatePi( pNtk, Buffer );
}
}
if ( Abc_NtkPoNum(pNtk) == 0 )
{
if ( nOutputs == -1 )
{
printf( "%s: The number of outputs is not specified.\n", Extra_FileReaderGetFileName(p) );
Abc_NtkDelete( pNtk );
return NULL;
}
nDigits = Extra_Base10Log( nOutputs );
for ( i = 0; i < nOutputs; i++ )
{
sprintf( Buffer, "z%0*d", nDigits, i );
Io_ReadCreatePo( pNtk, Buffer );
}
}
if ( Abc_NtkNodeNum(pNtk) == 0 )
{ // first time here
// create the PO drivers and add them
// start the SOP covers
ppSops = ALLOC( Vec_Str_t *, nOutputs );
Abc_NtkForEachPo( pNtk, pTermPo, i )
{
ppSops[i] = Vec_StrAlloc( 100 );
// create the node
pNode = Abc_NtkCreateNode(pNtk);
// connect the node to the PO net
Abc_ObjAddFanin( Abc_ObjFanin0Ntk(pTermPo), pNode );
// connect the node to the PI nets
Abc_NtkForEachPi( pNtk, pTermPi, k )
Abc_ObjAddFanin( pNode, Abc_ObjFanout0Ntk(pTermPi) );
}
}
// read the cubes
if ( vTokens->nSize != 2 )
{
printf( "%s (line %d): Input and output cubes are not specified.\n",
Extra_FileReaderGetFileName(p), iLine+1 );
Abc_NtkDelete( pNtk );
return NULL;
}
pCubeIn = vTokens->pArray[0];
pCubeOut = vTokens->pArray[1];
if ( strlen(pCubeIn) != (unsigned)nInputs )
{
printf( "%s (line %d): Input cube length (%d) differs from the number of inputs (%d).\n",
Extra_FileReaderGetFileName(p), iLine+1, strlen(pCubeIn), nInputs );
Abc_NtkDelete( pNtk );
return NULL;
}
if ( strlen(pCubeOut) != (unsigned)nOutputs )
{
printf( "%s (line %d): Output cube length (%d) differs from the number of outputs (%d).\n",
Extra_FileReaderGetFileName(p), iLine+1, strlen(pCubeOut), nOutputs );
Abc_NtkDelete( pNtk );
return NULL;
}
for ( i = 0; i < nOutputs; i++ )
{
if ( pCubeOut[i] == '1' )
{
Vec_StrAppend( ppSops[i], pCubeIn );
Vec_StrAppend( ppSops[i], " 1\n" );
}
}
nCubes++;
}
Abc_Ntk_t * My_Command_Associative(Abc_Ntk_t * pNtk)
{// check abc.h and abcNtk.c(Abc_ntkDup, duplication) freeXXX
//a new network to return
printf("inside the My_Command_Associative\n");
Abc_Ntk_t * new_pNtk;
Abc_Obj_t * pObj;
int i, j,k,m;
int changed = 0;
//check partial nodes satisfying a certain associative law
Abc_NtkForEachObj( pNtk, pObj, i)
{
//printf("Node ID: %d \n", Abc_ObjId(pObj));
//printf("FanInNum: %d \n",Abc_ObjFaninNum(pObj));
if(changed <1 && Abc_ObjFaninNum(pObj) == 2 && !Abc_ObjFaninC0(pObj) && !Abc_ObjFaninC1(pObj) )
{
Abc_Obj_t * pFanin_0 = Abc_ObjFanin0(pObj);
Abc_Obj_t * pFanin_1 = Abc_ObjFanin1(pObj);
// (x*y)*z => x*(y*z)
if(changed <1 && Abc_ObjFaninNum(pFanin_0) == 2 && !Abc_ObjFaninC0(pFanin_0) && !Abc_ObjFaninC1(pFanin_0) ) // (x*y)*z => x*(y*z)
{
printf("1st Condition, Node ID: %d\n",Abc_ObjId(pObj) );
printf("Abc_ObjFaninNum(pFanin_0): Node ID: %d\n",Abc_ObjId(pFanin_0) );
Abc_Obj_t * tempObj;
Abc_Obj_t * pFanin_0_0 = Abc_ObjFanin0(pFanin_0);
Abc_Obj_t * pFanin_0_1 = Abc_ObjFanin1(pFanin_0);
Abc_Obj_t * NewParentNode = Abc_NtkDupObj(pNtk, pObj, 1);
Abc_Obj_t * NewChildNode = Abc_NtkDupObj(pNtk, pFanin_0, 1);
int FanoutNum = Abc_ObjFanoutNum(pObj);
for (j=0; j<FanoutNum; j++)
{
tempObj = Abc_ObjFanout(pObj, j);
Abc_ObjDeleteFanin( tempObj , pObj );
Abc_ObjAddFanin( tempObj, NewParentNode);
}
printf("ParentNode Created and connected\n" );
Abc_ObjAddFanin(NewParentNode,pFanin_0_0 );
Abc_ObjAddFanin( NewParentNode, NewChildNode );
Abc_ObjAddFanin( NewChildNode, pFanin_0_1);
Abc_ObjAddFanin(NewChildNode,pFanin_1 );
printf("ChildNode Created and connected\n" );
printf("Abc_ObjFanoutNum(pFanin_0): %d\n",Abc_ObjFanoutNum(pFanin_0) );
if(Abc_ObjFanoutNum(pFanin_0)>1)
{
printf("pFanin_0 's FanOut > 1\n" );
}
else
{
Abc_ObjForEachFanin(pFanin_0,tempObj, k )
{
Abc_ObjDeleteFanin(pFanin_0,tempObj);
}
Abc_NtkDeleteObj(pFanin_0);
}
Abc_ObjForEachFanin(pObj,tempObj, k )
{
Abc_ObjDeleteFanin(pObj,tempObj);
}
/**Function*************************************************************
Synopsis [Implements the given retiming on the sequential AIG.]
Description [Returns 0 of initial state computation fails.]
SideEffects []
SeeAlso []
***********************************************************************/
int Seq_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int fVerbose )
{
Seq_RetEdge_t RetEdge;
stmm_table * tTable;
stmm_generator * gen;
Vec_Int_t * vValues;
Abc_Ntk_t * pNtkProb, * pNtkMiter, * pNtkCnf;
Abc_Obj_t * pNode, * pNodeNew;
int * pModel, RetValue, i, clk;
// return if the retiming is trivial
if ( Vec_PtrSize(vMoves) == 0 )
return 1;
// create the network for the initial state computation
// start the table and the array of PO values
pNtkProb = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 );
tTable = stmm_init_table( stmm_numcmp, stmm_numhash );
vValues = Vec_IntAlloc( 100 );
// perform the backward moves and build the network for initial state computation
RetValue = 0;
Vec_PtrForEachEntry( vMoves, pNode, i )
RetValue |= Abc_ObjRetimeBackward( pNode, pNtkProb, tTable, vValues );
// add the PIs corresponding to the white spots
stmm_foreach_item( tTable, gen, (char **)&RetEdge, (char **)&pNodeNew )
Abc_ObjAddFanin( pNodeNew, Abc_NtkCreatePi(pNtkProb) );
// add the PI/PO names
Abc_NtkAddDummyPiNames( pNtkProb );
Abc_NtkAddDummyPoNames( pNtkProb );
Abc_NtkAddDummyAssertNames( pNtkProb );
// make sure everything is okay with the network structure
if ( !Abc_NtkDoCheck( pNtkProb ) )
{
printf( "Seq_NtkImplementRetimingBackward: The internal network check has failed.\n" );
Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
Abc_NtkDelete( pNtkProb );
stmm_free_table( tTable );
Vec_IntFree( vValues );
return 0;
}
// check if conflict is found
if ( RetValue )
{
printf( "Seq_NtkImplementRetimingBackward: A top level conflict is detected. DC latch values are used.\n" );
Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
Abc_NtkDelete( pNtkProb );
stmm_free_table( tTable );
Vec_IntFree( vValues );
return 0;
}
// get the miter cone
pNtkMiter = Abc_NtkCreateTarget( pNtkProb, pNtkProb->vCos, vValues );
Abc_NtkDelete( pNtkProb );
Vec_IntFree( vValues );
if ( fVerbose )
printf( "The number of ANDs in the AIG = %5d.\n", Abc_NtkNodeNum(pNtkMiter) );
// transform the miter into a logic network for efficient CNF construction
// pNtkCnf = Abc_Ntk_Renode( pNtkMiter, 0, 100, 1, 0, 0 );
// Abc_NtkDelete( pNtkMiter );
pNtkCnf = pNtkMiter;
// solve the miter
clk = clock();
// RetValue = Abc_NtkMiterSat_OldAndRusty( pNtkCnf, 30, 0 );
RetValue = Abc_NtkMiterSat( pNtkCnf, (sint64)500000, (sint64)50000000, 0, 0, NULL, NULL );
if ( fVerbose )
if ( clock() - clk > 100 )
{
PRT( "SAT solving time", clock() - clk );
}
pModel = pNtkCnf->pModel; pNtkCnf->pModel = NULL;
Abc_NtkDelete( pNtkCnf );
// analyze the result
if ( RetValue == -1 || RetValue == 1 )
{
Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
if ( RetValue == 1 )
printf( "Seq_NtkImplementRetimingBackward: The problem is unsatisfiable. DC latch values are used.\n" );
else
printf( "Seq_NtkImplementRetimingBackward: The SAT problem timed out. DC latch values are used.\n" );
stmm_free_table( tTable );
return 0;
}
// set the values of the latches
Abc_NtkRetimeSetInitialValues( pNtk, tTable, pModel );
stmm_free_table( tTable );
free( pModel );
return 1;
}
ABC_NAMESPACE_IMPL_START
// For description of Binary BLIF format, refer to "abc/src/aig/bbl/bblif.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Fnction*************************************************************
Synopsis [Constructs ABC network from the manager.]
Description [The ABC network is started, as well as the array vCopy,
which will map the new ID of each object in the BBLIF manager into
the ponter ot the corresponding object in the ABC. For each internal
node, determined by Bbl_ObjIsLut(), the SOP representation is created
by retrieving the SOP representation of the BBLIF object. Finally,
the objects are connected using fanin/fanout creation, and the dummy
names are assigned because ABC requires each CI/CO to have a name.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Bbl_ManToAbc( Bbl_Man_t * p )
{
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObjNew;
Bbl_Obj_t * pObj, * pFanin;
Vec_Ptr_t * vCopy;
// start the network
pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 );
pNtk->pName = Extra_UtilStrsav( Bbl_ManName(p) );
// create objects
vCopy = Vec_PtrStart( 1000 );
Bbl_ManForEachObj( p, pObj )
{
if ( Bbl_ObjIsInput(pObj) )
pObjNew = Abc_NtkCreatePi( pNtk );
else if ( Bbl_ObjIsOutput(pObj) )
pObjNew = Abc_NtkCreatePo( pNtk );
else if ( Bbl_ObjIsLut(pObj) )
pObjNew = Abc_NtkCreateNode( pNtk );
else assert( 0 );
if ( Bbl_ObjIsLut(pObj) )
pObjNew->pData = Abc_SopRegister( (Mem_Flex_t *)pNtk->pManFunc, Bbl_ObjSop(p, pObj) );
Vec_PtrSetEntry( vCopy, Bbl_ObjId(pObj), pObjNew );
}
// connect objects
Bbl_ManForEachObj( p, pObj )
Bbl_ObjForEachFanin( pObj, pFanin )
Abc_ObjAddFanin( (Abc_Obj_t *)Vec_PtrEntry(vCopy, Bbl_ObjId(pObj)), (Abc_Obj_t *)Vec_PtrEntry(vCopy, Bbl_ObjId(pFanin)) );
// finalize
Vec_PtrFree( vCopy );
Abc_NtkAddDummyPiNames( pNtk );
Abc_NtkAddDummyPoNames( pNtk );
if ( !Abc_NtkCheck( pNtk ) )
printf( "Bbl_ManToAbc(): Network check has failed.\n" );
return pNtk;
}
/**Function*************************************************************
Synopsis [Maps virtual latches into real latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Seq_NtkShareLatches_rec( Abc_Ntk_t * pNtk, Abc_Obj_t * pObj, Seq_Lat_t * pRing, int nLatch, stmm_table * tLatchMap )
{
Abc_Obj_t * pLatch, * pFanin;
Abc_InitType_t Init;
unsigned Key;
if ( nLatch == 0 )
return pObj;
assert( pRing->pLatch == NULL );
// get the latch on the previous level
pFanin = Seq_NtkShareLatches_rec( pNtk, pObj, Seq_LatNext(pRing), nLatch - 1, tLatchMap );
// get the initial state
Init = Seq_LatInit( pRing );
// check if the latch with this initial state exists
Key = Seq_NtkShareLatchesKey( pFanin, Init );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
return pRing->pLatch = pLatch;
// does not exist
if ( Init != ABC_INIT_DC )
{
// check if the don't-care exists
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_DC );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) ) // yes
{
// update the table
stmm_delete( tLatchMap, (char **)&Key, (char **)&pLatch );
Key = Seq_NtkShareLatchesKey( pFanin, Init );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
// change don't-care to the given value
pLatch->pData = (void *)Init;
return pRing->pLatch = pLatch;
}
// add the latch with this value
pLatch = Abc_NtkCreateLatch( pNtk );
pLatch->pData = (void *)Init;
Abc_ObjAddFanin( pLatch, pFanin );
// add it to the table
Key = Seq_NtkShareLatchesKey( pFanin, Init );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
return pRing->pLatch = pLatch;
}
// the init value is the don't-care
// check if care values exist
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_ZERO );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
{
Seq_LatSetInit( pRing, ABC_INIT_ZERO );
return pRing->pLatch = pLatch;
}
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_ONE );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
{
Seq_LatSetInit( pRing, ABC_INIT_ONE );
return pRing->pLatch = pLatch;
}
// create the don't-care latch
pLatch = Abc_NtkCreateLatch( pNtk );
pLatch->pData = (void *)ABC_INIT_DC;
Abc_ObjAddFanin( pLatch, pFanin );
// add it to the table
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_DC );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
return pRing->pLatch = pLatch;
}
/**Function*************************************************************
Synopsis [Structurally hashes the given window.]
Description [The first PO is the observability condition. The second
is the node's function. The remaining POs are the candidate divisors.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Res_WndStrash( Res_Win_t * p )
{
Vec_Ptr_t * vPairs;
Abc_Ntk_t * pAig;
Abc_Obj_t * pObj, * pMiter;
int i;
assert( Abc_NtkHasAig(p->pNode->pNtk) );
// Abc_NtkCleanCopy( p->pNode->pNtk );
// create the network
pAig = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
pAig->pName = Extra_UtilStrsav( "window" );
// create the inputs
Vec_PtrForEachEntry( Abc_Obj_t *, p->vLeaves, pObj, i )
pObj->pCopy = Abc_NtkCreatePi( pAig );
Vec_PtrForEachEntry( Abc_Obj_t *, p->vBranches, pObj, i )
pObj->pCopy = Abc_NtkCreatePi( pAig );
// go through the nodes in the topological order
Vec_PtrForEachEntry( Abc_Obj_t *, p->vNodes, pObj, i )
{
pObj->pCopy = Abc_ConvertAigToAig( pAig, pObj );
if ( pObj == p->pNode )
pObj->pCopy = Abc_ObjNot( pObj->pCopy );
}
// collect the POs
vPairs = Vec_PtrAlloc( 2 * Vec_PtrSize(p->vRoots) );
Vec_PtrForEachEntry( Abc_Obj_t *, p->vRoots, pObj, i )
{
Vec_PtrPush( vPairs, pObj->pCopy );
Vec_PtrPush( vPairs, NULL );
}
// mark the TFO of the node
Abc_NtkIncrementTravId( p->pNode->pNtk );
Res_WinSweepLeafTfo_rec( p->pNode, (int)p->pNode->Level + p->nWinTfoMax );
// update strashing of the node
p->pNode->pCopy = Abc_ObjNot( p->pNode->pCopy );
Abc_NodeSetTravIdPrevious( p->pNode );
// redo strashing in the TFO
Vec_PtrForEachEntry( Abc_Obj_t *, p->vNodes, pObj, i )
{
if ( Abc_NodeIsTravIdCurrent(pObj) )
pObj->pCopy = Abc_ConvertAigToAig( pAig, pObj );
}
// collect the POs
Vec_PtrForEachEntry( Abc_Obj_t *, p->vRoots, pObj, i )
Vec_PtrWriteEntry( vPairs, 2 * i + 1, pObj->pCopy );
// add the miter
pMiter = Abc_AigMiter( (Abc_Aig_t *)pAig->pManFunc, vPairs, 0 );
Abc_ObjAddFanin( Abc_NtkCreatePo(pAig), pMiter );
Vec_PtrFree( vPairs );
// add the node
Abc_ObjAddFanin( Abc_NtkCreatePo(pAig), p->pNode->pCopy );
// add the fanins
Abc_ObjForEachFanin( p->pNode, pObj, i )
Abc_ObjAddFanin( Abc_NtkCreatePo(pAig), pObj->pCopy );
// add the divisors
Vec_PtrForEachEntry( Abc_Obj_t *, p->vDivs, pObj, i )
Abc_ObjAddFanin( Abc_NtkCreatePo(pAig), pObj->pCopy );
// add the names
Abc_NtkAddDummyPiNames( pAig );
Abc_NtkAddDummyPoNames( pAig );
// check the resulting network
if ( !Abc_NtkCheck( pAig ) )
fprintf( stdout, "Res_WndStrash(): Network check has failed.\n" );
return pAig;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_ReadEdifNetwork( Extra_FileReader_t * p )
{
ProgressBar * pProgress;
Vec_Ptr_t * vTokens;
Abc_Ntk_t * pNtk;
Abc_Obj_t * pNet, * pObj, * pFanout;
char * pGateName, * pNetName;
int fTokensReady, iLine, i;
// read the first line
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
if ( strcmp( (char *)vTokens->pArray[0], "edif" ) != 0 )
{
printf( "%s: Wrong input file format.\n", Extra_FileReaderGetFileName(p) );
return NULL;
}
// allocate the empty network
pNtk = Abc_NtkStartRead( Extra_FileReaderGetFileName(p) );
// go through the lines of the file
fTokensReady = 0;
pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p) );
for ( iLine = 1; fTokensReady || (vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p)); iLine++ )
{
Extra_ProgressBarUpdate( pProgress, Extra_FileReaderGetCurPosition(p), NULL );
// get the type of the line
fTokensReady = 0;
if ( strcmp( (char *)vTokens->pArray[0], "instance" ) == 0 )
{
pNetName = (char *)vTokens->pArray[1];
pNet = Abc_NtkFindOrCreateNet( pNtk, pNetName );
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
pGateName = (char *)vTokens->pArray[1];
if ( strncmp( pGateName, "Flip", 4 ) == 0 )
{
pObj = Abc_NtkCreateLatch( pNtk );
Abc_LatchSetInit0( pObj );
}
else
{
pObj = Abc_NtkCreateNode( pNtk );
// pObj->pData = Abc_NtkRegisterName( pNtk, pGateName );
pObj->pData = Extra_UtilStrsav( pGateName ); // memory leak!!!
}
Abc_ObjAddFanin( pNet, pObj );
}
else if ( strcmp( (char *)vTokens->pArray[0], "net" ) == 0 )
{
pNetName = (char *)vTokens->pArray[1];
if ( strcmp( pNetName, "CK" ) == 0 || strcmp( pNetName, "RESET" ) == 0 )
continue;
if ( strcmp( pNetName + strlen(pNetName) - 4, "_out" ) == 0 )
pNetName[strlen(pNetName) - 4] = 0;
pNet = Abc_NtkFindNet( pNtk, pNetName );
assert( pNet );
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
while ( strcmp( (char *)vTokens->pArray[0], "portRef" ) == 0 )
{
if ( strcmp( pNetName, (char *)vTokens->pArray[3] ) != 0 )
{
pFanout = Abc_NtkFindNet( pNtk, (char *)vTokens->pArray[3] );
Abc_ObjAddFanin( Abc_ObjFanin0(pFanout), pNet );
}
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
}
fTokensReady = 1;
}
else if ( strcmp( (char *)vTokens->pArray[0], "library" ) == 0 )
{
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
while ( strcmp( (char *)vTokens->pArray[0], "port" ) == 0 )
{
pNetName = (char *)vTokens->pArray[1];
if ( strcmp( pNetName, "CK" ) == 0 || strcmp( pNetName, "RESET" ) == 0 )
{
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
continue;
}
if ( strcmp( pNetName + strlen(pNetName) - 3, "_PO" ) == 0 )
pNetName[strlen(pNetName) - 3] = 0;
if ( strcmp( (char *)vTokens->pArray[3], "INPUT" ) == 0 )
Io_ReadCreatePi( pNtk, (char *)vTokens->pArray[1] );
else if ( strcmp( (char *)vTokens->pArray[3], "OUTPUT" ) == 0 )
Io_ReadCreatePo( pNtk, (char *)vTokens->pArray[1] );
else
{
printf( "%s (line %d): Wrong interface specification.\n", Extra_FileReaderGetFileName(p), iLine );
Abc_NtkDelete( pNtk );
return NULL;
}
vTokens = (Vec_Ptr_t *)Extra_FileReaderGetTokens(p);
}
}
else if ( strcmp( (char *)vTokens->pArray[0], "design" ) == 0 )
{
ABC_FREE( pNtk->pName );
pNtk->pName = (char *)Extra_UtilStrsav( (char *)vTokens->pArray[3] );
break;
}
}
Extra_ProgressBarStop( pProgress );
// assign logic functions
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( strncmp( (char *)pObj->pData, "And", 3 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateAnd((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj), NULL) );
else if ( strncmp( (char *)pObj->pData, "Or", 2 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateOr((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj), NULL) );
else if ( strncmp( (char *)pObj->pData, "Nand", 4 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateNand((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj)) );
else if ( strncmp( (char *)pObj->pData, "Nor", 3 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateNor((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj)) );
else if ( strncmp( (char *)pObj->pData, "Exor", 4 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateXor((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj)) );
else if ( strncmp( (char *)pObj->pData, "Exnor", 5 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateNxor((Mem_Flex_t *)pNtk->pManFunc, Abc_ObjFaninNum(pObj)) );
else if ( strncmp( (char *)pObj->pData, "Inv", 3 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateInv((Mem_Flex_t *)pNtk->pManFunc) );
else if ( strncmp( (char *)pObj->pData, "Buf", 3 ) == 0 )
Abc_ObjSetData( pObj, Abc_SopCreateBuf((Mem_Flex_t *)pNtk->pManFunc) );
else
{
printf( "%s: Unknown gate type \"%s\".\n", Extra_FileReaderGetFileName(p), (char*)pObj->pData );
Abc_NtkDelete( pNtk );
return NULL;
}
}
// check if constants have been added
// if ( pNet = Abc_NtkFindNet( pNtk, "VDD" ) )
// Io_ReadCreateConst( pNtk, "VDD", 1 );
// if ( pNet = Abc_NtkFindNet( pNtk, "GND" ) )
// Io_ReadCreateConst( pNtk, "GND", 0 );
Abc_NtkFinalizeRead( pNtk );
return pNtk;
}
