ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Copies the topmost levels of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NtkSensitivityMiter_rec( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode )
{
assert( !Abc_ObjIsComplement(pNode) );
if ( pNode->pCopy )
return pNode->pCopy;
Abc_NtkSensitivityMiter_rec( pNtkNew, Abc_ObjFanin0(pNode) );
Abc_NtkSensitivityMiter_rec( pNtkNew, Abc_ObjFanin1(pNode) );
return pNode->pCopy = Abc_AigAnd( (Abc_Aig_t *)pNtkNew->pManFunc, Abc_ObjChild0Copy(pNode), Abc_ObjChild1Copy(pNode) );
}
/**Function*************************************************************
Synopsis [Maps virtual latches into real latches.]
Description [Creates new latches and assigns them to virtual latches
on the edges of a sequential AIG. The nodes of the new network should
be created before this procedure is called.]
SideEffects []
SeeAlso []
***********************************************************************/
void Seq_NtkShareLatches( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj, * pFanin;
stmm_table * tLatchMap;
int i;
assert( Abc_NtkIsSeq( pNtk ) );
tLatchMap = stmm_init_table( stmm_ptrcmp, stmm_ptrhash );
Abc_AigForEachAnd( pNtk, pObj, i )
{
pFanin = Abc_ObjFanin0(pObj);
Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,0), Seq_NodeCountLats(pObj,0), tLatchMap );
pFanin = Abc_ObjFanin1(pObj);
Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,1), Seq_NodeCountLats(pObj,1), tLatchMap );
}
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
for ( pNext = pObj? pObj->pCopy : pObj; pObj; pObj = pNext, pNext = pObj? pObj->pCopy : pObj )
{
pFanin = Abc_ObjFanin0(pObj);
if ( !Abc_NodeIsTravIdCurrent(pFanin) )
pFanin->pData = Abc_NtkSensitivityMiter_rec( pMiter, pFanin );
pFanin = Abc_ObjFanin1(pObj);
if ( !Abc_NodeIsTravIdCurrent(pFanin) )
pFanin->pData = Abc_NtkSensitivityMiter_rec( pMiter, pFanin );
pObj->pCopy = Abc_AigAnd( (Abc_Aig_t *)pMiter->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild1Copy(pObj) );
pObj->pData = Abc_AigAnd( (Abc_Aig_t *)pMiter->pManFunc, Abc_ObjChild0Data(pObj), Abc_ObjChild1Data(pObj) );
}
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned Abc_Ntk4VarObj( Vec_Ptr_t * vNodes )
{
Abc_Obj_t * pObj;
unsigned uTruth0, uTruth1;
int i;
Vec_PtrForEachEntry( vNodes, pObj, i )
{
uTruth0 = (unsigned)(Abc_ObjFanin0(pObj)->pCopy);
uTruth1 = (unsigned)(Abc_ObjFanin1(pObj)->pCopy);
if ( Abc_ObjFaninC0(pObj) )
uTruth0 = ~uTruth0;
if ( Abc_ObjFaninC1(pObj) )
uTruth1 = ~uTruth1;
pObj->pCopy = (void *)(uTruth0 & uTruth1);
}
Vec_PtrForEachEntry( vNodes, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
// add the node to the mapper
pNodeFpga = Fpga_NodeAnd( pMan,
Fpga_NotCond( Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) ),
Fpga_NotCond( Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) ) );
assert( pNode->pCopy == NULL );
// remember the node
pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
if ( pSwitching )
Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
{
Fpga_NodeSetNextE( (Fpga_Node_t *)pPrev->pCopy, (Fpga_Node_t *)pFanin->pCopy );
Fpga_NodeSetRepr( (Fpga_Node_t *)pFanin->pCopy, (Fpga_Node_t *)pNode->pCopy );
}
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_Ntk4VarObjPrint_rec( Abc_Obj_t * pObj )
{
if ( pObj == Abc_AigConst1(pObj->pNtk) )
{
printf( "1" );
return;
}
if ( Abc_ObjIsPi(pObj) )
{
printf( "%c", pObj->Id - 1 + 'a' );
return;
}
printf( "(" );
Abc_Ntk4VarObjPrint_rec( Abc_ObjFanin0(pObj) );
if ( Abc_ObjFaninC0(pObj) )
printf( "\'" );
Abc_Ntk4VarObjPrint_rec( Abc_ObjFanin1(pObj) );
if ( Abc_ObjFaninC1(pObj) )
printf( "\'" );
printf( ")" );
}
int Abc_NodeFanin1Copy2( Abc_Obj_t * pObj )
{
return Abc_LitNotCond( Abc_ObjFanin1(pObj)->iTemp, Abc_ObjFaninC1(pObj) );
}
static inline int Abc_ObjGetXsimFanin1( Abc_Obj_t * pObj )
{
int RetValue;
RetValue = Abc_ObjGetXsim(Abc_ObjFanin1(pObj));
return Abc_ObjFaninC1(pObj)? Abc_XsimInv(RetValue) : RetValue;
}
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Man_t * Abc_NtkToMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, float * pSwitching, int fVerbose )
{
Map_Man_t * pMan;
Map_Node_t * pNodeMap;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Map_ManCreate( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, fVerbose );
if ( pMan == NULL )
return NULL;
Map_ManSetAreaRecovery( pMan, fRecovery );
Map_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
Map_ManSetDelayTarget( pMan, (float)DelayTarget );
Map_ManSetInputArrivals( pMan, Abc_NtkMapCopyCiArrival(pNtk, Abc_NtkGetCiArrivalTimes(pNtk)) );
Map_ManSetOutputRequireds( pMan, Abc_NtkMapCopyCoRequired(pNtk, Abc_NtkGetCoRequiredTimes(pNtk)) );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Map_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i == Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
}
// load the AIG into the mapper
vNodes = Abc_AigDfsMap( pNtk );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
{
if ( Abc_ObjIsLatch(pNode) )
{
pFanin = Abc_ObjFanin0(pNode);
pNodeMap = Map_NodeBuf( pMan, Map_NotCond( Abc_ObjFanin0(pFanin)->pCopy, (int)Abc_ObjFaninC0(pFanin) ) );
Abc_ObjFanout0(pNode)->pCopy = (Abc_Obj_t *)pNodeMap;
continue;
}
assert( Abc_ObjIsNode(pNode) );
// add the node to the mapper
pNodeMap = Map_NodeAnd( pMan,
Map_NotCond( Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) ),
Map_NotCond( Abc_ObjFanin1(pNode)->pCopy, (int)Abc_ObjFaninC1(pNode) ) );
assert( pNode->pCopy == NULL );
// remember the node
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = (Abc_Obj_t *)pNode->pData; pFanin; pPrev = pFanin, pFanin = (Abc_Obj_t *)pFanin->pData )
{
Map_NodeSetNextE( (Map_Node_t *)pPrev->pCopy, (Map_Node_t *)pFanin->pCopy );
Map_NodeSetRepr( (Map_Node_t *)pFanin->pCopy, (Map_Node_t *)pNode->pCopy );
}
}
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
Vec_PtrFree( vNodes );
// set the primary outputs in the required phase
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i == Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
Map_ManReadOutputs(pMan)[i] = Map_NotCond( (Map_Node_t *)Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) );
}
return pMan;
}
Abc_Ntk_t * My_Command_Associative(Abc_Ntk_t * pNtk)
{// check abc.h and abcNtk.c(Abc_ntkDup, duplication) freeXXX
//a new network to return
printf("inside the My_Command_Associative\n");
Abc_Ntk_t * new_pNtk;
Abc_Obj_t * pObj;
int i, j,k,m;
int changed = 0;
//check partial nodes satisfying a certain associative law
Abc_NtkForEachObj( pNtk, pObj, i)
{
//printf("Node ID: %d \n", Abc_ObjId(pObj));
//printf("FanInNum: %d \n",Abc_ObjFaninNum(pObj));
if(changed <1 && Abc_ObjFaninNum(pObj) == 2 && !Abc_ObjFaninC0(pObj) && !Abc_ObjFaninC1(pObj) )
{
Abc_Obj_t * pFanin_0 = Abc_ObjFanin0(pObj);
Abc_Obj_t * pFanin_1 = Abc_ObjFanin1(pObj);
// (x*y)*z => x*(y*z)
if(changed <1 && Abc_ObjFaninNum(pFanin_0) == 2 && !Abc_ObjFaninC0(pFanin_0) && !Abc_ObjFaninC1(pFanin_0) ) // (x*y)*z => x*(y*z)
{
printf("1st Condition, Node ID: %d\n",Abc_ObjId(pObj) );
printf("Abc_ObjFaninNum(pFanin_0): Node ID: %d\n",Abc_ObjId(pFanin_0) );
Abc_Obj_t * tempObj;
Abc_Obj_t * pFanin_0_0 = Abc_ObjFanin0(pFanin_0);
Abc_Obj_t * pFanin_0_1 = Abc_ObjFanin1(pFanin_0);
Abc_Obj_t * NewParentNode = Abc_NtkDupObj(pNtk, pObj, 1);
Abc_Obj_t * NewChildNode = Abc_NtkDupObj(pNtk, pFanin_0, 1);
int FanoutNum = Abc_ObjFanoutNum(pObj);
for (j=0; j<FanoutNum; j++)
{
tempObj = Abc_ObjFanout(pObj, j);
Abc_ObjDeleteFanin( tempObj , pObj );
Abc_ObjAddFanin( tempObj, NewParentNode);
}
printf("ParentNode Created and connected\n" );
Abc_ObjAddFanin(NewParentNode,pFanin_0_0 );
Abc_ObjAddFanin( NewParentNode, NewChildNode );
Abc_ObjAddFanin( NewChildNode, pFanin_0_1);
Abc_ObjAddFanin(NewChildNode,pFanin_1 );
printf("ChildNode Created and connected\n" );
printf("Abc_ObjFanoutNum(pFanin_0): %d\n",Abc_ObjFanoutNum(pFanin_0) );
if(Abc_ObjFanoutNum(pFanin_0)>1)
{
printf("pFanin_0 's FanOut > 1\n" );
}
else
{
Abc_ObjForEachFanin(pFanin_0,tempObj, k )
{
Abc_ObjDeleteFanin(pFanin_0,tempObj);
}
Abc_NtkDeleteObj(pFanin_0);
}
Abc_ObjForEachFanin(pObj,tempObj, k )
{
Abc_ObjDeleteFanin(pObj,tempObj);
}
