ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts old ABC network into new ABC network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Abc_NtkToNtkNew( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Nwk_Man_t * pNtkNew;
Nwk_Obj_t * pObjNew;
Abc_Obj_t * pObj, * pFanin;
int i, k;
if ( !Abc_NtkIsLogic(pNtk) )
{
fprintf( stdout, "This is not a logic network.\n" );
return 0;
}
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// construct the network
pNtkNew = Nwk_ManAlloc();
pNtkNew->pName = Extra_UtilStrsav( pNtk->pName );
pNtkNew->pSpec = Extra_UtilStrsav( pNtk->pSpec );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Nwk_ManCreateCi( pNtkNew, Abc_ObjFanoutNum(pObj) );
vNodes = Abc_NtkDfs( pNtk, 1 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
pObjNew = Nwk_ManCreateNode( pNtkNew, Abc_ObjFaninNum(pObj), Abc_ObjFanoutNum(pObj) );
Abc_ObjForEachFanin( pObj, pFanin, k )
Nwk_ObjAddFanin( pObjNew, (Nwk_Obj_t *)pFanin->pCopy );
pObjNew->pFunc = Hop_Transfer( (Hop_Man_t *)pNtk->pManFunc, pNtkNew->pManHop, (Hop_Obj_t *)pObj->pData, Abc_ObjFaninNum(pObj) );
pObj->pCopy = (Abc_Obj_t *)pObjNew;
}
/**Function*************************************************************
Synopsis [Returns the array of nodes to be combined into one multi-input AND-gate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkCollectSupergate_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vSuper, int fFirst, int fStopAtMux )
{
int RetValue1, RetValue2, i;
// check if the node is visited
if ( Abc_ObjRegular(pNode)->fMarkB )
{
// check if the node occurs in the same polarity
for ( i = 0; i < vSuper->nSize; i++ )
if ( vSuper->pArray[i] == pNode )
return 1;
// check if the node is present in the opposite polarity
for ( i = 0; i < vSuper->nSize; i++ )
if ( vSuper->pArray[i] == Abc_ObjNot(pNode) )
return -1;
assert( 0 );
return 0;
}
// if the new node is complemented or a PI, another gate begins
if ( !fFirst )
if ( Abc_ObjIsComplement(pNode) || !Abc_ObjIsNode(pNode) || Abc_ObjFanoutNum(pNode) > 1 || (fStopAtMux && Abc_NodeIsMuxType(pNode)) )
{
Vec_PtrPush( vSuper, pNode );
Abc_ObjRegular(pNode)->fMarkB = 1;
return 0;
}
assert( !Abc_ObjIsComplement(pNode) );
assert( Abc_ObjIsNode(pNode) );
// go through the branches
RetValue1 = Abc_NtkCollectSupergate_rec( Abc_ObjChild0(pNode), vSuper, 0, fStopAtMux );
RetValue2 = Abc_NtkCollectSupergate_rec( Abc_ObjChild1(pNode), vSuper, 0, fStopAtMux );
if ( RetValue1 == -1 || RetValue2 == -1 )
return -1;
// return 1 if at least one branch has a duplicate
return RetValue1 || RetValue2;
}
/**Function*************************************************************
Synopsis [Checks integraty of the manager.]
Description [Checks if there are gates that are not used by any primary output.
If no such gates exist, return 1 else return 0.]
SideEffects []
SeeAlso []
***********************************************************************/
int ABC_Check_Integrity( ABC_Manager mng )
{
Abc_Ntk_t * pNtk = mng->pNtk;
Abc_Obj_t * pObj;
int i;
// check that there are no dangling nodes
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( i == 0 )
continue;
if ( Abc_ObjFanoutNum(pObj) == 0 )
{
// printf( "ABC_Check_Integrity: The network has dangling nodes.\n" );
return 0;
}
}
// make sure everything is okay with the network structure
if ( !Abc_NtkDoCheck( pNtk ) )
{
printf( "ABC_Check_Integrity: The internal network check has failed.\n" );
return 0;
}
return 1;
}
void Abc_NtkPrintFanoutProfile( Abc_Obj_t * pObj )
{
Abc_Obj_t * pFanout;
int i;
printf( "Obj %6d fanouts (%d):\n", Abc_ObjId(pObj), Abc_ObjFanoutNum(pObj) );
Abc_ObjForEachFanout( pObj, pFanout, i )
{
printf( "%3d : time = %7.2f ps load = %7.2f ff ", i, Bus_SclObjETime(pFanout), Bus_SclObjCin(pFanout) );
printf( "%s\n", Abc_ObjFaninPhase( pFanout, Abc_NodeFindFanin(pFanout, pObj) ) ? "*" : " " );
}
/**Function*************************************************************
Synopsis [Transfers fanout from the old node to the new node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_ObjTransferFanout( Abc_Obj_t * pNodeFrom, Abc_Obj_t * pNodeTo )
{
Vec_Ptr_t * vFanouts;
int nFanoutsOld, i;
assert( !Abc_ObjIsComplement(pNodeFrom) );
assert( !Abc_ObjIsComplement(pNodeTo) );
assert( !Abc_ObjIsPo(pNodeFrom) && !Abc_ObjIsPo(pNodeTo) );
assert( pNodeFrom->pNtk == pNodeTo->pNtk );
assert( pNodeFrom != pNodeTo );
assert( Abc_ObjFanoutNum(pNodeFrom) > 0 );
// get the fanouts of the old node
nFanoutsOld = Abc_ObjFanoutNum(pNodeTo);
vFanouts = Vec_PtrAlloc( nFanoutsOld );
Abc_NodeCollectFanouts( pNodeFrom, vFanouts );
// patch the fanin of each of them
for ( i = 0; i < vFanouts->nSize; i++ )
Abc_ObjPatchFanin( vFanouts->pArray[i], pNodeFrom, pNodeTo );
assert( Abc_ObjFanoutNum(pNodeFrom) == 0 );
assert( Abc_ObjFanoutNum(pNodeTo) == nFanoutsOld + vFanouts->nSize );
Vec_PtrFree( vFanouts );
}
float Abc_NtkComputeNodeLoad( Bus_Man_t * p, Abc_Obj_t * pObj )
{
Abc_Obj_t * pFanout;
float Load;
int i;
assert( Bus_SclObjLoad(pObj) == 0 );
Load = Abc_SclFindWireLoad( p->vWireCaps, Abc_ObjFanoutNum(pObj) );
Abc_ObjForEachFanout( pObj, pFanout, i )
Load += Bus_SclObjCin( pFanout );
Bus_SclObjSetLoad( pObj, Load );
return Load;
}
/**Function*************************************************************
Synopsis [Replaces the node by a new node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_ObjReplace( Abc_Obj_t * pNodeOld, Abc_Obj_t * pNodeNew )
{
assert( !Abc_ObjIsComplement(pNodeOld) );
assert( !Abc_ObjIsComplement(pNodeNew) );
assert( pNodeOld->pNtk == pNodeNew->pNtk );
assert( pNodeOld != pNodeNew );
assert( Abc_ObjFanoutNum(pNodeOld) > 0 );
// transfer the fanouts to the old node
Abc_ObjTransferFanout( pNodeOld, pNodeNew );
// remove the old node
Abc_NtkDeleteObj_rec( pNodeOld, 1 );
}
/**Function*************************************************************
Synopsis [Updates the net.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Abc_PlaceUpdateNet( Abc_Obj_t * pObj )
{
Abc_Obj_t * pFanout;
int k;
// free the old array of net terminals
if ( nets[pObj->Id].m_terms )
free( nets[pObj->Id].m_terms );
// fill in the net with the new information
nets[pObj->Id].m_id = pObj->Id;
nets[pObj->Id].m_weight = 1.0;
nets[pObj->Id].m_numTerms = Abc_ObjFanoutNum(pObj); //fanout
nets[pObj->Id].m_terms = ALLOC(ConcreteCell*, Abc_ObjFanoutNum(pObj));
Abc_ObjForEachFanout( pObj, pFanout, k )
nets[pObj->Id].m_terms[k] = &(cells[pFanout->Id]);
addConcreteNet(&(nets[pObj->Id]));
}
/**Function*************************************************************
Synopsis [Tranfers names to the old network.]
Description [Assumes that the new nodes are attached using pObj->pCopy.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTrasferNamesNoLatches( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
Abc_Obj_t * pObj;
int i;
assert( Abc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkNew) );
assert( Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkNew) );
assert( Nm_ManNumEntries(pNtk->pManName) > 0 );
assert( Nm_ManNumEntries(pNtkNew->pManName) == 0 );
// copy the CI/CO/box name and skip latches and theirs inputs/outputs
Abc_NtkForEachCi( pNtk, pObj, i )
if ( Abc_ObjFaninNum(pObj) == 0 || !Abc_ObjIsLatch(Abc_ObjFanin0(pObj)) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanout0Ntk(pObj)), NULL );
Abc_NtkForEachCo( pNtk, pObj, i )
if ( Abc_ObjFanoutNum(pObj) == 0 || !Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL );
Abc_NtkForEachBox( pNtk, pObj, i )
if ( !Abc_ObjIsLatch(pObj) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(pObj), NULL );
}
/**Function*************************************************************
Synopsis [Selects the best cut to represent the node in the mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Cut_Cut_t * Seq_FpgaMappingSelectCut( Abc_Obj_t * pAnd )
{
Abc_Obj_t * pFanin;
Cut_Cut_t * pCut, * pCutBest, * pList;
float CostCur, CostMin = ABC_INFINITY;
int ArrivalCut, ArrivalMin, i;
// get the arrival time of the best non-trivial cut
ArrivalMin = Seq_NodeGetLValue( pAnd );
// iterate through the cuts and select the one with the minimum cost
pList = Abc_NodeReadCuts( Seq_NodeCutMan(pAnd), pAnd );
CostMin = ABC_INFINITY;
pCutBest = NULL;
for ( pCut = pList->pNext; pCut; pCut = pCut->pNext )
{
ArrivalCut = *((int *)&pCut->uSign);
// assert( ArrivalCut >= ArrivalMin );
if ( ArrivalCut > ArrivalMin )
continue;
CostCur = 0.0;
for ( i = 0; i < (int)pCut->nLeaves; i++ )
{
pFanin = Abc_NtkObj( pAnd->pNtk, pCut->pLeaves[i] >> 8 );
if ( Abc_ObjIsPi(pFanin) )
continue;
if ( Abc_NodeIsTravIdCurrent(pFanin) )
continue;
CostCur += (float)(1.0 / Abc_ObjFanoutNum(pFanin));
// CostCur += Seq_NodeGetFlow( pFanin );
}
if ( CostMin > CostCur )
{
CostMin = CostCur;
pCutBest = pCut;
}
}
assert( pCutBest != NULL );
return pCutBest;
}
/**Function*************************************************************
Synopsis [Prepares the network for retiming.]
Description [Hash latches into their number in the original network.]
SideEffects []
SeeAlso []
***********************************************************************/
st__table * Abc_NtkRetimePrepareLatches( Abc_Ntk_t * pNtk )
{
st__table * tLatches;
Abc_Obj_t * pLatch, * pLatchIn, * pLatchOut, * pFanin;
int i, nOffSet = Abc_NtkBoxNum(pNtk) - Abc_NtkLatchNum(pNtk);
// collect latches and remove CIs/COs
tLatches = st__init_table( st__ptrcmp, st__ptrhash );
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
// map latch into its true number
st__insert( tLatches, (char *)(ABC_PTRUINT_T)pLatch, (char *)(ABC_PTRUINT_T)(i-nOffSet) );
// disconnect LI
pLatchIn = Abc_ObjFanin0(pLatch);
pFanin = Abc_ObjFanin0(pLatchIn);
Abc_ObjTransferFanout( pLatchIn, pFanin );
Abc_ObjDeleteFanin( pLatchIn, pFanin );
// disconnect LO
pLatchOut = Abc_ObjFanout0(pLatch);
pFanin = Abc_ObjFanin0(pLatchOut);
if ( Abc_ObjFanoutNum(pLatchOut) > 0 )
Abc_ObjTransferFanout( pLatchOut, pFanin );
Abc_ObjDeleteFanin( pLatchOut, pFanin );
}
/**Function*************************************************************
Synopsis [Transforms the node to take fanout sharing into account.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Seq_NodeShareFanouts( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
{
Abc_Obj_t * pFanout;
Abc_InitType_t Type;
int nLatches[4], i;
// skip the node with only one fanout
if ( Abc_ObjFanoutNum(pNode) < 2 )
return;
// clean the the fanout counters
for ( i = 0; i < 4; i++ )
nLatches[i] = 0;
// find the number of fanouts having latches of each type
Abc_ObjForEachFanout( pNode, pFanout, i )
{
if ( Seq_ObjFanoutL(pNode, pFanout) == 0 )
continue;
Type = Seq_NodeGetInitLast( pFanout, Abc_ObjFanoutEdgeNum(pNode, pFanout) );
nLatches[Type]++;
}
// decide what to do
if ( nLatches[ABC_INIT_ZERO] > 1 && nLatches[ABC_INIT_ONE] > 1 ) // 0-group and 1-group
{
Seq_NodeShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
Seq_NodeShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
}
else if ( nLatches[ABC_INIT_ZERO] > 1 ) // 0-group
Seq_NodeShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
else if ( nLatches[ABC_INIT_ONE] > 1 ) // 1-group
Seq_NodeShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
else if ( nLatches[ABC_INIT_DC] > 1 ) // DC-group
{
if ( nLatches[ABC_INIT_ZERO] > 0 )
Seq_NodeShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
else
Seq_NodeShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
}
}
/**Function*************************************************************
Synopsis [Transforms the AIG into nodes.]
Description [Threhold is the max number of nodes duplicated at a node.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkMultiInt( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
ProgressBar * pProgress;
Abc_Obj_t * pNode, * pConst1, * pNodeNew;
int i;
// set the constant node
pConst1 = Abc_AigConst1(pNtk);
if ( Abc_ObjFanoutNum(pConst1) > 0 )
{
pNodeNew = Abc_NtkCreateNode( pNtkNew );
pNodeNew->pData = Cudd_ReadOne( pNtkNew->pManFunc ); Cudd_Ref( pNodeNew->pData );
pConst1->pCopy = pNodeNew;
}
// perform renoding for POs
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
Abc_NtkForEachCo( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( Abc_ObjIsCi(Abc_ObjFanin0(pNode)) )
continue;
Abc_NtkMulti_rec( pNtkNew, Abc_ObjFanin0(pNode) );
}
/**Function*************************************************************
Synopsis [Performs rewriting for one node.]
Description [This procedure considers all the cuts computed for the node
and tries to rewrite each of them using the "forest" of different AIG
structures precomputed and stored in the RWR manager.
Determines the best rewriting and computes the gain in the number of AIG
nodes in the final network. In the end, p->vFanins contains information
about the best cut that can be used for rewriting, while p->pGraph gives
the decomposition dag (represented using decomposition graph data structure).
Returns gain in the number of nodes or -1 if node cannot be rewritten.]
SideEffects []
SeeAlso []
***********************************************************************/
int Rwr_NodeRewrite( Rwr_Man_t * p, Cut_Man_t * pManCut, Abc_Obj_t * pNode, int fUpdateLevel, int fUseZeros, int fPlaceEnable )
{
int fVeryVerbose = 0;
Dec_Graph_t * pGraph;
Cut_Cut_t * pCut;//, * pTemp;
Abc_Obj_t * pFanin;
unsigned uPhase, uTruthBest, uTruth;
char * pPerm;
int Required, nNodesSaved, nNodesSaveCur;
int i, GainCur, GainBest = -1;
int clk, clk2;//, Counter;
p->nNodesConsidered++;
// get the required times
Required = fUpdateLevel? Abc_ObjRequiredLevel(pNode) : ABC_INFINITY;
// get the node's cuts
clk = clock();
pCut = (Cut_Cut_t *)Abc_NodeGetCutsRecursive( pManCut, pNode, 0, 0 );
assert( pCut != NULL );
p->timeCut += clock() - clk;
//printf( " %d", Rwr_CutCountNumNodes(pNode, pCut) );
/*
Counter = 0;
for ( pTemp = pCut->pNext; pTemp; pTemp = pTemp->pNext )
Counter++;
printf( "%d ", Counter );
*/
// go through the cuts
clk = clock();
for ( pCut = pCut->pNext; pCut; pCut = pCut->pNext )
{
// consider only 4-input cuts
if ( pCut->nLeaves < 4 )
continue;
// Cut_CutPrint( pCut, 0 ), printf( "\n" );
// get the fanin permutation
uTruth = 0xFFFF & *Cut_CutReadTruth(pCut);
pPerm = p->pPerms4[ p->pPerms[uTruth] ];
uPhase = p->pPhases[uTruth];
// collect fanins with the corresponding permutation/phase
Vec_PtrClear( p->vFaninsCur );
Vec_PtrFill( p->vFaninsCur, (int)pCut->nLeaves, 0 );
for ( i = 0; i < (int)pCut->nLeaves; i++ )
{
pFanin = Abc_NtkObj( pNode->pNtk, pCut->pLeaves[pPerm[i]] );
if ( pFanin == NULL )
break;
pFanin = Abc_ObjNotCond(pFanin, ((uPhase & (1<<i)) > 0) );
Vec_PtrWriteEntry( p->vFaninsCur, i, pFanin );
}
if ( i != (int)pCut->nLeaves )
{
p->nCutsBad++;
continue;
}
p->nCutsGood++;
{
int Counter = 0;
Vec_PtrForEachEntry( p->vFaninsCur, pFanin, i )
if ( Abc_ObjFanoutNum(Abc_ObjRegular(pFanin)) == 1 )
Counter++;
if ( Counter > 2 )
continue;
}
clk2 = clock();
/*
printf( "Considering: (" );
Vec_PtrForEachEntry( p->vFaninsCur, pFanin, i )
printf( "%d ", Abc_ObjFanoutNum(Abc_ObjRegular(pFanin)) );
printf( ")\n" );
*/
// mark the fanin boundary
Vec_PtrForEachEntry( p->vFaninsCur, pFanin, i )
Abc_ObjRegular(pFanin)->vFanouts.nSize++;
// label MFFC with current ID
Abc_NtkIncrementTravId( pNode->pNtk );
nNodesSaved = Abc_NodeMffcLabelAig( pNode );
// unmark the fanin boundary
Vec_PtrForEachEntry( p->vFaninsCur, pFanin, i )
Abc_ObjRegular(pFanin)->vFanouts.nSize--;
p->timeMffc += clock() - clk2;
// evaluate the cut
clk2 = clock();
pGraph = Rwr_CutEvaluate( p, pNode, pCut, p->vFaninsCur, nNodesSaved, Required, &GainCur, fPlaceEnable );
p->timeEval += clock() - clk2;
// check if the cut is better than the current best one
if ( pGraph != NULL && GainBest < GainCur )
{
// save this form
nNodesSaveCur = nNodesSaved;
GainBest = GainCur;
p->pGraph = pGraph;
p->fCompl = ((uPhase & (1<<4)) > 0);
uTruthBest = 0xFFFF & *Cut_CutReadTruth(pCut);
// collect fanins in the
Vec_PtrClear( p->vFanins );
Vec_PtrForEachEntry( p->vFaninsCur, pFanin, i )
Vec_PtrPush( p->vFanins, pFanin );
}
}
p->timeRes += clock() - clk;
if ( GainBest == -1 )
return -1;
/*
if ( GainBest > 0 )
{
printf( "Class %d ", p->pMap[uTruthBest] );
printf( "Gain = %d. Node %d : ", GainBest, pNode->Id );
Vec_PtrForEachEntry( p->vFanins, pFanin, i )
printf( "%d ", Abc_ObjRegular(pFanin)->Id );
Dec_GraphPrint( stdout, p->pGraph, NULL, NULL );
printf( "\n" );
}
*/
// printf( "%d", nNodesSaveCur - GainBest );
/*
if ( GainBest > 0 )
{
if ( Rwr_CutIsBoolean( pNode, p->vFanins ) )
printf( "b" );
else
{
printf( "Node %d : ", pNode->Id );
Vec_PtrForEachEntry( p->vFanins, pFanin, i )
printf( "%d ", Abc_ObjRegular(pFanin)->Id );
printf( "a" );
}
}
*/
/*
if ( GainBest > 0 )
if ( p->fCompl )
printf( "c" );
else
printf( "." );
*/
// copy the leaves
Vec_PtrForEachEntry( p->vFanins, pFanin, i )
Dec_GraphNode(p->pGraph, i)->pFunc = pFanin;
/*
printf( "(" );
Vec_PtrForEachEntry( p->vFanins, pFanin, i )
printf( " %d", Abc_ObjRegular(pFanin)->vFanouts.nSize - 1 );
printf( " ) " );
*/
// printf( "%d ", Rwr_NodeGetDepth_rec( pNode, p->vFanins ) );
p->nScores[p->pMap[uTruthBest]]++;
p->nNodesGained += GainBest;
if ( fUseZeros || GainBest > 0 )
{
p->nNodesRewritten++;
}
// report the progress
if ( fVeryVerbose && GainBest > 0 )
{
printf( "Node %6s : ", Abc_ObjName(pNode) );
printf( "Fanins = %d. ", p->vFanins->nSize );
printf( "Save = %d. ", nNodesSaveCur );
printf( "Add = %d. ", nNodesSaveCur-GainBest );
printf( "GAIN = %d. ", GainBest );
printf( "Cone = %d. ", p->pGraph? Dec_GraphNodeNum(p->pGraph) : 0 );
printf( "Class = %d. ", p->pMap[uTruthBest] );
printf( "\n" );
}
return GainBest;
}
/**Function*************************************************************
Synopsis [Performs incremental rewriting of the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose, int fVeryVerbose, int fPlaceEnable )
{
extern void Dec_GraphUpdateNetwork( Abc_Obj_t * pRoot, Dec_Graph_t * pGraph, int fUpdateLevel, int nGain );
ProgressBar * pProgress;
Cut_Man_t * pManCut;
Rwr_Man_t * pManRwr;
Abc_Obj_t * pNode;
// Vec_Ptr_t * vAddedCells = NULL, * vUpdatedNets = NULL;
Dec_Graph_t * pGraph;
int i, nNodes, nGain, fCompl;
abctime clk, clkStart = Abc_Clock();
assert( Abc_NtkIsStrash(pNtk) );
// cleanup the AIG
Abc_AigCleanup((Abc_Aig_t *)pNtk->pManFunc);
/*
{
Vec_Vec_t * vParts;
vParts = Abc_NtkPartitionSmart( pNtk, 50, 1 );
Vec_VecFree( vParts );
}
*/
// start placement package
// if ( fPlaceEnable )
// {
// Abc_PlaceBegin( pNtk );
// vAddedCells = Abc_AigUpdateStart( pNtk->pManFunc, &vUpdatedNets );
// }
// start the rewriting manager
pManRwr = Rwr_ManStart( 0 );
if ( pManRwr == NULL )
return 0;
// compute the reverse levels if level update is requested
if ( fUpdateLevel )
Abc_NtkStartReverseLevels( pNtk, 0 );
// start the cut manager
clk = Abc_Clock();
pManCut = Abc_NtkStartCutManForRewrite( pNtk );
Rwr_ManAddTimeCuts( pManRwr, Abc_Clock() - clk );
pNtk->pManCut = pManCut;
if ( fVeryVerbose )
Rwr_ScoresClean( pManRwr );
// resynthesize each node once
pManRwr->nNodesBeg = Abc_NtkNodeNum(pNtk);
nNodes = Abc_NtkObjNumMax(pNtk);
pProgress = Extra_ProgressBarStart( stdout, nNodes );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
// stop if all nodes have been tried once
if ( i >= nNodes )
break;
// skip persistant nodes
if ( Abc_NodeIsPersistant(pNode) )
continue;
// skip the nodes with many fanouts
if ( Abc_ObjFanoutNum(pNode) > 1000 )
continue;
// for each cut, try to resynthesize it
nGain = Rwr_NodeRewrite( pManRwr, pManCut, pNode, fUpdateLevel, fUseZeros, fPlaceEnable );
if ( !(nGain > 0 || (nGain == 0 && fUseZeros)) )
continue;
// if we end up here, a rewriting step is accepted
// get hold of the new subgraph to be added to the AIG
pGraph = (Dec_Graph_t *)Rwr_ManReadDecs(pManRwr);
fCompl = Rwr_ManReadCompl(pManRwr);
// reset the array of the changed nodes
if ( fPlaceEnable )
Abc_AigUpdateReset( (Abc_Aig_t *)pNtk->pManFunc );
// complement the FF if needed
if ( fCompl ) Dec_GraphComplement( pGraph );
clk = Abc_Clock();
Dec_GraphUpdateNetwork( pNode, pGraph, fUpdateLevel, nGain );
Rwr_ManAddTimeUpdate( pManRwr, Abc_Clock() - clk );
if ( fCompl ) Dec_GraphComplement( pGraph );
// use the array of changed nodes to update placement
// if ( fPlaceEnable )
// Abc_PlaceUpdate( vAddedCells, vUpdatedNets );
}
/**Function*************************************************************
Synopsis [Writes the graph structure of network for DOT.]
Description [Useful for graph visualization using tools such as GraphViz:
http://www.graphviz.org/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse )
{
FILE * pFile;
Abc_Obj_t * pNode, * pFanin;
char * pSopString;
int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds, fCompl;
int Limit = 300;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( vNodes->nSize < 1 )
{
printf( "The set has no nodes. DOT file is not written.\n" );
return;
}
if ( vNodes->nSize > Limit )
{
printf( "The set has more than %d nodes. DOT file is not written.\n", Limit );
return;
}
// start the stream
if ( (pFile = fopen( pFileName, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", pFileName );
return;
}
// transform logic functions from BDD to SOP
if ( fHasBdds = Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
{
printf( "Io_WriteDotNtk(): Converting to SOPs has failed.\n" );
return;
}
}
// mark the nodes from the set
Vec_PtrForEachEntry( vNodes, pNode, i )
pNode->fMarkC = 1;
if ( vNodesShow )
Vec_PtrForEachEntry( vNodesShow, pNode, i )
pNode->fMarkB = 1;
// get the levels of nodes
LevelMax = Abc_NtkLevel( pNtk );
if ( fUseReverse )
{
LevelMin = Abc_NtkLevelReverse( pNtk );
assert( LevelMax == LevelMin );
Vec_PtrForEachEntry( vNodes, pNode, i )
if ( Abc_ObjIsNode(pNode) )
pNode->Level = LevelMax - pNode->Level + 1;
}
// find the largest and the smallest levels
LevelMin = 10000;
LevelMax = -1;
fHasCos = 0;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
{
fHasCos = 1;
continue;
}
if ( LevelMin > (int)pNode->Level )
LevelMin = pNode->Level;
if ( LevelMax < (int)pNode->Level )
LevelMax = pNode->Level;
}
// set the level of the CO nodes
if ( fHasCos )
{
LevelMax++;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
pNode->Level = LevelMax;
}
}
// write the DOT header
fprintf( pFile, "# %s\n", "Network structure generated by ABC" );
fprintf( pFile, "\n" );
fprintf( pFile, "digraph network {\n" );
fprintf( pFile, "size = \"7.5,10\";\n" );
// fprintf( pFile, "size = \"10,8.5\";\n" );
// fprintf( pFile, "size = \"14,11\";\n" );
// fprintf( pFile, "page = \"8,11\";\n" );
// fprintf( pFile, "ranksep = 0.5;\n" );
// fprintf( pFile, "nodesep = 0.5;\n" );
fprintf( pFile, "center = true;\n" );
// fprintf( pFile, "orientation = landscape;\n" );
// fprintf( pFile, "edge [fontsize = 10];\n" );
// fprintf( pFile, "edge [dir = none];\n" );
fprintf( pFile, "edge [dir = back];\n" );
fprintf( pFile, "\n" );
// labels on the left of the picture
fprintf( pFile, "{\n" );
fprintf( pFile, " node [shape = plaintext];\n" );
fprintf( pFile, " edge [style = invis];\n" );
fprintf( pFile, " LevelTitle1 [label=\"\"];\n" );
fprintf( pFile, " LevelTitle2 [label=\"\"];\n" );
// generate node names with labels
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
fprintf( pFile, " [label = " );
// label name
fprintf( pFile, "\"" );
fprintf( pFile, "\"" );
fprintf( pFile, "];\n" );
}
// genetate the sequence of visible/invisible nodes to mark levels
fprintf( pFile, " LevelTitle1 -> LevelTitle2 ->" );
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
// the connector
if ( Level != LevelMin )
fprintf( pFile, " ->" );
else
fprintf( pFile, ";" );
}
fprintf( pFile, "\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate title box on top
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle1;\n" );
fprintf( pFile, " title1 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=20,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
fprintf( pFile, "%s", "Network structure visualized by ABC" );
fprintf( pFile, "\\n" );
fprintf( pFile, "Benchmark \\\"%s\\\". ", pNtk->pName );
fprintf( pFile, "Time was %s. ", Extra_TimeStamp() );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate statistics box
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle2;\n" );
fprintf( pFile, " title2 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=18,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
if ( Abc_NtkObjNum(pNtk) == Vec_PtrSize(vNodes) )
fprintf( pFile, "The network contains %d logic nodes and %d latches.", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk) );
else
fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
fprintf( pFile, "\\n" );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate the POs
if ( fHasCos )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMax );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCo(pNode) )
continue;
fprintf( pFile, " Node%d [label = \"%s%s\"",
pNode->Id,
(Abc_ObjIsBi(pNode)? Abc_ObjName(Abc_ObjFanout0(pNode)):Abc_ObjName(pNode)),
(Abc_ObjIsBi(pNode)? "_in":"") );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBi(pNode)? "box":"invtriangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate nodes of each rank
for ( Level = LevelMax - fHasCos; Level >= LevelMin && Level > 0; Level-- )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", Level );
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( (int)pNode->Level != Level )
continue;
if ( Abc_ObjFaninNum(pNode) == 0 )
continue;
// fprintf( pFile, " Node%d [label = \"%d\"", pNode->Id, pNode->Id );
if ( Abc_NtkIsStrash(pNtk) )
pSopString = "";
else if ( Abc_NtkHasMapping(pNtk) && fGateNames )
pSopString = Mio_GateReadName(pNode->pData);
else if ( Abc_NtkHasMapping(pNtk) )
pSopString = Abc_NtkPrintSop(Mio_GateReadSop(pNode->pData));
else
pSopString = Abc_NtkPrintSop(pNode->pData);
fprintf( pFile, " Node%d [label = \"%d\\n%s\"", pNode->Id, pNode->Id, pSopString );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate the PI nodes if any
if ( LevelMin == 0 )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMin );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCi(pNode) )
{
// check if the costant node is present
if ( Abc_ObjFaninNum(pNode) == 0 && Abc_ObjFanoutNum(pNode) > 0 )
{
fprintf( pFile, " Node%d [label = \"Const%d\"", pNode->Id, Abc_NtkIsStrash(pNode->pNtk) || Abc_NodeIsConst1(pNode) );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
continue;
}
fprintf( pFile, " Node%d [label = \"%s\"",
pNode->Id,
(Abc_ObjIsBo(pNode)? Abc_ObjName(Abc_ObjFanin0(pNode)):Abc_ObjName(pNode)) );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBo(pNode)? "box":"triangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
/**Function*************************************************************
Synopsis [Performs minimum-register retiming.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t *
Abc_FlowRetime_MinReg( Abc_Ntk_t * pNtk, int fVerbose,
int fComputeInitState, int fGuaranteeInitState, int fBlockConst,
int fForwardOnly, int fBackwardOnly, int nMaxIters,
int maxDelay, int fFastButConservative ) {
int i;
Abc_Obj_t *pObj, *pNext;
InitConstraint_t *pData;
// create manager
pManMR = ALLOC( MinRegMan_t, 1 );
pManMR->pNtk = pNtk;
pManMR->fVerbose = fVerbose;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fGuaranteeInitState = fGuaranteeInitState;
pManMR->fBlockConst = fBlockConst;
pManMR->fForwardOnly = fForwardOnly;
pManMR->fBackwardOnly = fBackwardOnly;
pManMR->nMaxIters = nMaxIters;
pManMR->maxDelay = maxDelay;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fConservTimingOnly = fFastButConservative;
pManMR->vNodes = Vec_PtrAlloc(100);
pManMR->vInitConstraints = Vec_PtrAlloc(2);
pManMR->pInitNtk = NULL;
pManMR->pInitToOrig = NULL;
pManMR->sizeInitToOrig = 0;
vprintf("Flow-based minimum-register retiming...\n");
if (!Abc_NtkHasOnlyLatchBoxes(pNtk)) {
printf("\tERROR: Can not retime with black/white boxes\n");
return pNtk;
}
if (maxDelay) {
vprintf("\tmax delay constraint = %d\n", maxDelay);
if (maxDelay < (i = Abc_NtkLevel(pNtk))) {
printf("ERROR: max delay constraint (%d) must be > current max delay (%d)\n", maxDelay, i);
return pNtk;
}
}
// print info about type of network
vprintf("\tnetlist type = ");
if (Abc_NtkIsNetlist( pNtk )) { vprintf("netlist/"); }
else if (Abc_NtkIsLogic( pNtk )) { vprintf("logic/"); }
else if (Abc_NtkIsStrash( pNtk )) { vprintf("strash/"); }
else { vprintf("***unknown***/"); }
if (Abc_NtkHasSop( pNtk )) { vprintf("sop\n"); }
else if (Abc_NtkHasBdd( pNtk )) { vprintf("bdd\n"); }
else if (Abc_NtkHasAig( pNtk )) { vprintf("aig\n"); }
else if (Abc_NtkHasMapping( pNtk )) { vprintf("mapped\n"); }
else { vprintf("***unknown***\n"); }
vprintf("\tinitial reg count = %d\n", Abc_NtkLatchNum(pNtk));
vprintf("\tinitial levels = %d\n", Abc_NtkLevel(pNtk));
// remove bubbles from latch boxes
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
vprintf("\tpushing bubbles out of latch boxes\n");
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_FlowRetime_RemoveLatchBubbles(pObj);
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
// check for box inputs/outputs
Abc_NtkForEachLatch( pNtk, pObj, i ) {
assert(Abc_ObjFaninNum(pObj) == 1);
assert(Abc_ObjFanoutNum(pObj) == 1);
assert(!Abc_ObjFaninC0(pObj));
pNext = Abc_ObjFanin0(pObj);
assert(Abc_ObjIsBi(pNext));
assert(Abc_ObjFaninNum(pNext) <= 1);
if(Abc_ObjFaninNum(pNext) == 0) // every Bi should have a fanin
Abc_FlowRetime_AddDummyFanin( pNext );
pNext = Abc_ObjFanout0(pObj);
assert(Abc_ObjIsBo(pNext));
assert(Abc_ObjFaninNum(pNext) == 1);
assert(!Abc_ObjFaninC0(pNext));
}
/**Function*************************************************************
Synopsis [Performs rewriting for one node.]
Description [This procedure considers all the cuts computed for the node
and tries to rewrite each of them using the "forest" of different AIG
structures precomputed and stored in the RWR manager.
Determines the best rewriting and computes the gain in the number of AIG
nodes in the final network. In the end, p->vFanins contains information
about the best cut that can be used for rewriting, while p->pGraph gives
the decomposition dag (represented using decomposition graph data structure).
Returns gain in the number of nodes or -1 if node cannot be rewritten.]
SideEffects []
SeeAlso []
***********************************************************************/
int Rwr_NodeRewrite( Rwr_Man_t * p, Cut_Man_t * pManCut, Abc_Obj_t * pNode, int fUpdateLevel, int fUseZeros, int fPlaceEnable )
{
int fVeryVerbose = 0;
Dec_Graph_t * pGraph;
Cut_Cut_t * pCut;//, * pTemp;
Abc_Obj_t * pFanin;
unsigned uPhase;
unsigned uTruthBest = 0; // Suppress "might be used uninitialized"
unsigned uTruth;
char * pPerm;
int Required, nNodesSaved;
int nNodesSaveCur = -1; // Suppress "might be used uninitialized"
int i, GainCur, GainBest = -1;
int clk, clk2;//, Counter;
p->nNodesConsidered++;
// get the required times
Required = fUpdateLevel? Abc_ObjRequiredLevel(pNode) : ABC_INFINITY;
// get the node's cuts
clk = clock();
pCut = (Cut_Cut_t *)Abc_NodeGetCutsRecursive( pManCut, pNode, 0, 0 );
assert( pCut != NULL );
p->timeCut += clock() - clk;
//printf( " %d", Rwr_CutCountNumNodes(pNode, pCut) );
/*
Counter = 0;
for ( pTemp = pCut->pNext; pTemp; pTemp = pTemp->pNext )
Counter++;
printf( "%d ", Counter );
*/
// go through the cuts
clk = clock();
for ( pCut = pCut->pNext; pCut; pCut = pCut->pNext )
{
// consider only 4-input cuts
if ( pCut->nLeaves < 4 )
continue;
// Cut_CutPrint( pCut, 0 ), printf( "\n" );
// get the fanin permutation
uTruth = 0xFFFF & *Cut_CutReadTruth(pCut);
pPerm = p->pPerms4[ (int)p->pPerms[uTruth] ];
uPhase = p->pPhases[uTruth];
// collect fanins with the corresponding permutation/phase
Vec_PtrClear( p->vFaninsCur );
Vec_PtrFill( p->vFaninsCur, (int)pCut->nLeaves, 0 );
for ( i = 0; i < (int)pCut->nLeaves; i++ )
{
pFanin = Abc_NtkObj( pNode->pNtk, pCut->pLeaves[(int)pPerm[i]] );
if ( pFanin == NULL )
break;
pFanin = Abc_ObjNotCond(pFanin, ((uPhase & (1<<i)) > 0) );
Vec_PtrWriteEntry( p->vFaninsCur, i, pFanin );
}
if ( i != (int)pCut->nLeaves )
{
p->nCutsBad++;
continue;
}
p->nCutsGood++;
{
int Counter = 0;
Vec_PtrForEachEntry( Abc_Obj_t *, p->vFaninsCur, pFanin, i )
if ( Abc_ObjFanoutNum(Abc_ObjRegular(pFanin)) == 1 )
Counter++;
if ( Counter > 2 )
continue;
}
clk2 = clock();
/*
printf( "Considering: (" );
Vec_PtrForEachEntry( Abc_Obj_t *, p->vFaninsCur, pFanin, i )
printf( "%d ", Abc_ObjFanoutNum(Abc_ObjRegular(pFanin)) );
printf( ")\n" );
*/
// mark the fanin boundary
Vec_PtrForEachEntry( Abc_Obj_t *, p->vFaninsCur, pFanin, i )
Abc_ObjRegular(pFanin)->vFanouts.nSize++;
// label MFFC with current ID
Abc_NtkIncrementTravId( pNode->pNtk );
nNodesSaved = Abc_NodeMffcLabelAig( pNode );
// unmark the fanin boundary
Vec_PtrForEachEntry( Abc_Obj_t *, p->vFaninsCur, pFanin, i )
Abc_ObjRegular(pFanin)->vFanouts.nSize--;
p->timeMffc += clock() - clk2;
// evaluate the cut
clk2 = clock();
pGraph = Rwr_CutEvaluate( p, pNode, pCut, p->vFaninsCur, nNodesSaved, Required, &GainCur, fPlaceEnable );
p->timeEval += clock() - clk2;
// check if the cut is better than the current best one
if ( pGraph != NULL && GainBest < GainCur )
{
// save this form
nNodesSaveCur = nNodesSaved;
GainBest = GainCur;
p->pGraph = pGraph;
p->fCompl = ((uPhase & (1<<4)) > 0);
uTruthBest = 0xFFFF & *Cut_CutReadTruth(pCut);
// collect fanins in the
Vec_PtrClear( p->vFanins );
Vec_PtrForEachEntry( Abc_Obj_t *, p->vFaninsCur, pFanin, i )
Vec_PtrPush( p->vFanins, pFanin );
}
}
Abc_Ntk_t * My_Command_Associative(Abc_Ntk_t * pNtk)
{// check abc.h and abcNtk.c(Abc_ntkDup, duplication) freeXXX
//a new network to return
printf("inside the My_Command_Associative\n");
Abc_Ntk_t * new_pNtk;
Abc_Obj_t * pObj;
int i, j,k,m;
int changed = 0;
//check partial nodes satisfying a certain associative law
Abc_NtkForEachObj( pNtk, pObj, i)
{
//printf("Node ID: %d \n", Abc_ObjId(pObj));
//printf("FanInNum: %d \n",Abc_ObjFaninNum(pObj));
if(changed <1 && Abc_ObjFaninNum(pObj) == 2 && !Abc_ObjFaninC0(pObj) && !Abc_ObjFaninC1(pObj) )
{
Abc_Obj_t * pFanin_0 = Abc_ObjFanin0(pObj);
Abc_Obj_t * pFanin_1 = Abc_ObjFanin1(pObj);
// (x*y)*z => x*(y*z)
if(changed <1 && Abc_ObjFaninNum(pFanin_0) == 2 && !Abc_ObjFaninC0(pFanin_0) && !Abc_ObjFaninC1(pFanin_0) ) // (x*y)*z => x*(y*z)
{
printf("1st Condition, Node ID: %d\n",Abc_ObjId(pObj) );
printf("Abc_ObjFaninNum(pFanin_0): Node ID: %d\n",Abc_ObjId(pFanin_0) );
Abc_Obj_t * tempObj;
Abc_Obj_t * pFanin_0_0 = Abc_ObjFanin0(pFanin_0);
Abc_Obj_t * pFanin_0_1 = Abc_ObjFanin1(pFanin_0);
Abc_Obj_t * NewParentNode = Abc_NtkDupObj(pNtk, pObj, 1);
Abc_Obj_t * NewChildNode = Abc_NtkDupObj(pNtk, pFanin_0, 1);
int FanoutNum = Abc_ObjFanoutNum(pObj);
for (j=0; j<FanoutNum; j++)
{
tempObj = Abc_ObjFanout(pObj, j);
Abc_ObjDeleteFanin( tempObj , pObj );
Abc_ObjAddFanin( tempObj, NewParentNode);
}
printf("ParentNode Created and connected\n" );
Abc_ObjAddFanin(NewParentNode,pFanin_0_0 );
Abc_ObjAddFanin( NewParentNode, NewChildNode );
Abc_ObjAddFanin( NewChildNode, pFanin_0_1);
Abc_ObjAddFanin(NewChildNode,pFanin_1 );
printf("ChildNode Created and connected\n" );
printf("Abc_ObjFanoutNum(pFanin_0): %d\n",Abc_ObjFanoutNum(pFanin_0) );
if(Abc_ObjFanoutNum(pFanin_0)>1)
{
printf("pFanin_0 's FanOut > 1\n" );
}
else
{
Abc_ObjForEachFanin(pFanin_0,tempObj, k )
{
Abc_ObjDeleteFanin(pFanin_0,tempObj);
}
Abc_NtkDeleteObj(pFanin_0);
}
Abc_ObjForEachFanin(pObj,tempObj, k )
{
Abc_ObjDeleteFanin(pObj,tempObj);
}