/**Function*************************************************************
Synopsis [Creates the dual output miter.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManCreateDualOutputMiter( Aig_Man_t * p1, Aig_Man_t * p2 )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
assert( Aig_ManPiNum(p1) == Aig_ManPiNum(p2) );
assert( Aig_ManPoNum(p1) == Aig_ManPoNum(p2) );
pNew = Aig_ManStart( Aig_ManObjNumMax(p1) + Aig_ManObjNumMax(p2) );
// add first AIG
Aig_ManConst1(p1)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p1, pObj, i )
pObj->pData = Aig_ObjCreatePi( pNew );
Aig_ManForEachNode( p1, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add second AIG
Aig_ManConst1(p2)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p2, pObj, i )
pObj->pData = Aig_ManPi( pNew, i );
Aig_ManForEachNode( p2, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add the outputs
for ( i = 0; i < Aig_ManPoNum(p1); i++ )
{
Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(Aig_ManPo(p1, i)) );
Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(Aig_ManPo(p2, i)) );
}
Aig_ManCleanup( pNew );
return pNew;
}
/**Function*************************************************************
Synopsis [Derives CNF for the mapping.]
Description [The last argument shows the number of last outputs
of the manager, which will not be converted into clauses but the
new variables for which will be introduced.]
SideEffects []
SeeAlso []
***********************************************************************/
Cnf_Dat_t * Cnf_ManWriteCnf( Cnf_Man_t * p, Vec_Ptr_t * vMapped, int nOutputs )
{
Aig_Obj_t * pObj;
Cnf_Dat_t * pCnf;
Cnf_Cut_t * pCut;
Vec_Int_t * vCover, * vSopTemp;
int OutVar, PoVar, pVars[32], * pLits, ** pClas;
unsigned uTruth;
int i, k, nLiterals, nClauses, Cube, Number;
// count the number of literals and clauses
nLiterals = 1 + Aig_ManPoNum( p->pManAig ) + 3 * nOutputs;
nClauses = 1 + Aig_ManPoNum( p->pManAig ) + nOutputs;
Vec_PtrForEachEntry( vMapped, pObj, i )
{
assert( Aig_ObjIsNode(pObj) );
pCut = Cnf_ObjBestCut( pObj );
// positive polarity of the cut
if ( pCut->nFanins < 5 )
{
uTruth = 0xFFFF & *Cnf_CutTruth(pCut);
nLiterals += Cnf_SopCountLiterals( p->pSops[uTruth], p->pSopSizes[uTruth] ) + p->pSopSizes[uTruth];
assert( p->pSopSizes[uTruth] >= 0 );
nClauses += p->pSopSizes[uTruth];
}
else
{
nLiterals += Cnf_IsopCountLiterals( pCut->vIsop[1], pCut->nFanins ) + Vec_IntSize(pCut->vIsop[1]);
nClauses += Vec_IntSize(pCut->vIsop[1]);
}
// negative polarity of the cut
if ( pCut->nFanins < 5 )
{
uTruth = 0xFFFF & ~*Cnf_CutTruth(pCut);
nLiterals += Cnf_SopCountLiterals( p->pSops[uTruth], p->pSopSizes[uTruth] ) + p->pSopSizes[uTruth];
assert( p->pSopSizes[uTruth] >= 0 );
nClauses += p->pSopSizes[uTruth];
}
else
{
nLiterals += Cnf_IsopCountLiterals( pCut->vIsop[0], pCut->nFanins ) + Vec_IntSize(pCut->vIsop[0]);
nClauses += Vec_IntSize(pCut->vIsop[0]);
}
//printf( "%d ", nClauses-(1 + Aig_ManPoNum( p->pManAig )) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManTemporDecompose( Aig_Man_t * pAig, int nFrames )
{
Aig_Man_t * pAigNew, * pFrames;
Aig_Obj_t * pObj, * pReset;
int i;
if ( pAig->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// create initialized timeframes
pFrames = Saig_ManTemporFrames( pAig, nFrames );
assert( Aig_ManPoNum(pFrames) == Aig_ManRegNum(pAig) );
// start the new manager
Aig_ManCleanData( pAig );
pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
pAigNew->pName = Aig_UtilStrsav( pAig->pName );
// map the constant node and primary inputs
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pAigNew );
Saig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
// insert initialization logic
Aig_ManConst1(pFrames)->pData = Aig_ManConst1( pAigNew );
Aig_ManForEachPi( pFrames, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
Aig_ManForEachNode( pFrames, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_ManForEachPo( pFrames, pObj, i )
pObj->pData = Aig_ObjChild0Copy(pObj);
// create reset latch (the first one among the latches)
pReset = Aig_ObjCreatePi( pAigNew );
// create flop output values
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_Mux( pAigNew, pReset, Aig_ObjCreatePi(pAigNew), (Aig_Obj_t *)Aig_ManPo(pFrames, i)->pData );
Aig_ManStop( pFrames );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create primary outputs
Saig_ManForEachPo( pAig, pObj, i )
Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
// create reset latch (the first one among the latches)
Aig_ObjCreatePo( pAigNew, Aig_ManConst1(pAigNew) );
// create latch inputs
Saig_ManForEachLi( pAig, pObj, i )
Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
// finalize
Aig_ManCleanup( pAigNew );
Aig_ManSetRegNum( pAigNew, Aig_ManRegNum(pAig)+1 ); // + reset latch (011111...)
return pAigNew;
}
/**Function*************************************************************
Synopsis [Performs clock-gating for the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cgt_ClockGatingRangeCheck( Cgt_Man_t * p, int iStart, int nOutputs )
{
Vec_Ptr_t * vNodes = p->vFanout;
Aig_Obj_t * pMiter, * pCand, * pMiterFrame, * pCandFrame, * pMiterPart, * pCandPart;
int i, k, RetValue, nCalls;
assert( Vec_VecSize(p->vGatesAll) == Aig_ManPoNum(p->pFrame) );
// go through all the registers inputs of this range
for ( i = iStart; i < iStart + nOutputs; i++ )
{
nCalls = p->nCalls;
pMiter = Saig_ManLi( p->pAig, i );
Cgt_ManDetectCandidates( p->pAig, Aig_ObjFanin0(pMiter), p->pPars->nLevelMax, vNodes );
// go through the candidates of this PO
Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pCand, k )
{
// get the corresponding nodes from the frames
pCandFrame = (Aig_Obj_t *)pCand->pData;
pMiterFrame = (Aig_Obj_t *)pMiter->pData;
// get the corresponding nodes from the part
pCandPart = (Aig_Obj_t *)pCandFrame->pData;
pMiterPart = (Aig_Obj_t *)pMiterFrame->pData;
// try direct polarity
if ( Cgt_SimulationFilter( p, pCandPart, pMiterPart ) )
{
RetValue = Cgt_CheckImplication( p, pCandPart, pMiterPart );
if ( RetValue == 1 )
{
Vec_VecPush( p->vGatesAll, i, pCand );
continue;
}
if ( RetValue == 0 )
Cgt_SimulationRecord( p );
}
else
p->nCallsFiltered++;
// try reverse polarity
if ( Cgt_SimulationFilter( p, Aig_Not(pCandPart), pMiterPart ) )
{
RetValue = Cgt_CheckImplication( p, Aig_Not(pCandPart), pMiterPart );
if ( RetValue == 1 )
{
Vec_VecPush( p->vGatesAll, i, Aig_Not(pCand) );
continue;
}
if ( RetValue == 0 )
Cgt_SimulationRecord( p );
}
else
p->nCallsFiltered++;
}
if ( p->pPars->fVerbose )
{
// printf( "Flop %3d : Cand = %4d. Gate = %4d. SAT calls = %3d.\n",
// i, Vec_PtrSize(vNodes), Vec_PtrSize(Vec_VecEntry(p->vGatesAll, i)), p->nCalls-nCalls );
}
}
/**Function*************************************************************
Synopsis [Create the array of literals to be written.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Ioa_WriteAigerLiterals( Aig_Man_t * pMan )
{
Vec_Int_t * vLits;
Aig_Obj_t * pObj, * pDriver;
int i;
vLits = Vec_IntAlloc( Aig_ManPoNum(pMan) );
Aig_ManForEachLiSeq( pMan, pObj, i )
{
pDriver = Aig_ObjFanin0(pObj);
Vec_IntPush( vLits, Ioa_ObjMakeLit( Ioa_ObjAigerNum(pDriver), Aig_ObjFaninC0(pObj) ^ (Ioa_ObjAigerNum(pDriver) == 0) ) );
}
/**Function*************************************************************
Synopsis [Returns the shared size of global BDDs of the COs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_ManSizeOfGlobalBdds( Aig_Man_t * p )
{
Vec_Ptr_t * vFuncsGlob;
Aig_Obj_t * pObj;
int RetValue, i;
// complement the global functions
vFuncsGlob = Vec_PtrAlloc( Aig_ManPoNum(p) );
Aig_ManForEachPo( p, pObj, i )
Vec_PtrPush( vFuncsGlob, Aig_ObjGlobalBdd(pObj) );
RetValue = Cudd_SharingSize( (DdNode **)Vec_PtrArray(vFuncsGlob), Vec_PtrSize(vFuncsGlob) );
Vec_PtrFree( vFuncsGlob );
return RetValue;
}
/**Function*************************************************************
Synopsis [Converts AIG from Aig_Man_t into Hop_Obj_t.]
Description [Assumes that Aig_Man_t has exactly one primary outputs.
Returns the pointer to the root node (Hop_Obj_t) in Hop_Man_t.]
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_MfsConvertAigToHop( Aig_Man_t * pMan, Hop_Man_t * pHop )
{
Aig_Obj_t * pRoot, * pObj;
int i;
assert( Aig_ManPoNum(pMan) == 1 );
pRoot = Aig_ManPo( pMan, 0 );
// check the case of a constant
if ( Aig_ObjIsConst1( Aig_ObjFanin0(pRoot) ) )
return Hop_NotCond( Hop_ManConst1(pHop), Aig_ObjFaninC0(pRoot) );
// set the PI mapping
Aig_ManCleanData( pMan );
Aig_ManForEachPi( pMan, pObj, i )
pObj->pData = Hop_IthVar( pHop, i );
// construct the AIG
Abc_MfsConvertAigToHop_rec( Aig_ObjFanin0(pRoot), pHop );
return Hop_NotCond( (Hop_Obj_t *)Aig_ObjFanin0(pRoot)->pData, Aig_ObjFaninC0(pRoot) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Saig_ManDumpBlif( Aig_Man_t * p, char * pFileName )
{
FILE * pFile;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i;
if ( Aig_ManPoNum(p) == 0 )
{
printf( "Aig_ManDumpBlif(): AIG manager does not have POs.\n" );
return;
}
Aig_ManSetPioNumbers( p );
// write input file
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
printf( "Saig_ManDumpBlif(): Cannot open file for writing.\n" );
return;
}
fprintf( pFile, "# BLIF file written by procedure Saig_ManDumpBlif()\n" );
fprintf( pFile, "# If unedited, this file can be read by Saig_ManReadBlif()\n" );
fprintf( pFile, "# AIG stats: pi=%d po=%d reg=%d and=%d obj=%d maxid=%d\n",
Saig_ManPiNum(p), Saig_ManPoNum(p), Saig_ManRegNum(p),
Aig_ManNodeNum(p), Aig_ManObjNum(p), Aig_ManObjNumMax(p) );
fprintf( pFile, ".model %s\n", p->pName );
// write primary inputs
fprintf( pFile, ".inputs" );
Aig_ManForEachPiSeq( p, pObj, i )
fprintf( pFile, " %s", Saig_ObjName(p, pObj) );
fprintf( pFile, "\n" );
// write primary outputs
fprintf( pFile, ".outputs" );
Aig_ManForEachPoSeq( p, pObj, i )
fprintf( pFile, " %s", Saig_ObjName(p, pObj) );
fprintf( pFile, "\n" );
// write registers
if ( Aig_ManRegNum(p) )
{
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
{
fprintf( pFile, ".latch" );
fprintf( pFile, " %s", Saig_ObjName(p, pObjLi) );
fprintf( pFile, " %s", Saig_ObjName(p, pObjLo) );
fprintf( pFile, " 0\n" );
}
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Nwk_ManFromIf( If_Man_t * pIfMan, Aig_Man_t * p, Vec_Ptr_t * vAigToIf )
{
Vec_Ptr_t * vIfToAig;
Nwk_Man_t * pNtk;
Nwk_Obj_t * pObjNew;
Aig_Obj_t * pObj, * pObjRepr;
If_Obj_t * pIfObj;
If_Cut_t * pCutBest;
int i, k, nLeaves, * ppLeaves;
assert( Aig_ManPiNum(p) == If_ManCiNum(pIfMan) );
assert( Aig_ManPoNum(p) == If_ManCoNum(pIfMan) );
assert( Aig_ManNodeNum(p) == If_ManAndNum(pIfMan) );
Aig_ManCleanData( p );
If_ManCleanCutData( pIfMan );
// create mapping of IF to AIG
vIfToAig = Vec_PtrStart( If_ManObjNum(pIfMan) );
Aig_ManForEachObj( p, pObj, i )
{
pIfObj = (If_Obj_t *)Vec_PtrEntry( vAigToIf, i );
Vec_PtrWriteEntry( vIfToAig, pIfObj->Id, pObj );
}
/**Function*************************************************************
Synopsis [Performs induction by unrolling timeframes backward.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManInduction( Aig_Man_t * p, int nFramesMax, int nConfMax, int fUnique, int fUniqueAll, int fGetCex, int fVerbose, int fVeryVerbose )
{
sat_solver * pSat;
Aig_Man_t * pAigPart;
Cnf_Dat_t * pCnfPart;
Vec_Int_t * vTopVarNums, * vState, * vTopVarIds = NULL;
Vec_Ptr_t * vTop, * vBot;
Aig_Obj_t * pObjPi, * pObjPiCopy, * pObjPo;
int i, k, f, clk, Lits[2], status, RetValue, nSatVarNum, nConfPrev;
int nOldSize, iReg, iLast, fAdded, nConstrs = 0, nClauses = 0;
assert( fUnique == 0 || fUniqueAll == 0 );
assert( Saig_ManPoNum(p) == 1 );
Aig_ManSetPioNumbers( p );
// start the top by including the PO
vBot = Vec_PtrAlloc( 100 );
vTop = Vec_PtrAlloc( 100 );
vState = Vec_IntAlloc( 1000 );
Vec_PtrPush( vTop, Aig_ManPo(p, 0) );
// start the array of CNF variables
vTopVarNums = Vec_IntAlloc( 100 );
// start the solver
pSat = sat_solver_new();
sat_solver_setnvars( pSat, 1000 );
// iterate backward unrolling
RetValue = -1;
nSatVarNum = 0;
if ( fVerbose )
printf( "Induction parameters: FramesMax = %5d. ConflictMax = %6d.\n", nFramesMax, nConfMax );
for ( f = 0; ; f++ )
{
if ( f > 0 )
{
Aig_ManStop( pAigPart );
Cnf_DataFree( pCnfPart );
}
clk = clock();
// get the bottom
Aig_SupportNodes( p, (Aig_Obj_t **)Vec_PtrArray(vTop), Vec_PtrSize(vTop), vBot );
// derive AIG for the part between top and bottom
pAigPart = Aig_ManDupSimpleDfsPart( p, vBot, vTop );
// convert it into CNF
pCnfPart = Cnf_Derive( pAigPart, Aig_ManPoNum(pAigPart) );
Cnf_DataLift( pCnfPart, nSatVarNum );
nSatVarNum += pCnfPart->nVars;
nClauses += pCnfPart->nClauses;
// remember top frame var IDs
if ( fGetCex && vTopVarIds == NULL )
{
vTopVarIds = Vec_IntStartFull( Aig_ManPiNum(p) );
Aig_ManForEachPi( p, pObjPi, i )
{
if ( pObjPi->pData == NULL )
continue;
pObjPiCopy = (Aig_Obj_t *)pObjPi->pData;
assert( Aig_ObjIsPi(pObjPiCopy) );
if ( Saig_ObjIsPi(p, pObjPi) )
Vec_IntWriteEntry( vTopVarIds, Aig_ObjPioNum(pObjPi) + Saig_ManRegNum(p), pCnfPart->pVarNums[Aig_ObjId(pObjPiCopy)] );
else if ( Saig_ObjIsLo(p, pObjPi) )
Vec_IntWriteEntry( vTopVarIds, Aig_ObjPioNum(pObjPi) - Saig_ManPiNum(p), pCnfPart->pVarNums[Aig_ObjId(pObjPiCopy)] );
else assert( 0 );
}
}
// stitch variables of top and bot
assert( Aig_ManPoNum(pAigPart)-1 == Vec_IntSize(vTopVarNums) );
Aig_ManForEachPo( pAigPart, pObjPo, i )
{
if ( i == 0 )
{
// do not perform inductive strengthening
// if ( f > 0 )
// continue;
// add topmost literal
Lits[0] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], f>0 );
if ( !sat_solver_addclause( pSat, Lits, Lits+1 ) )
assert( 0 );
nClauses++;
continue;
}
Lits[0] = toLitCond( Vec_IntEntry(vTopVarNums, i-1), 0 );
Lits[1] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], 1 );
if ( !sat_solver_addclause( pSat, Lits, Lits+2 ) )
assert( 0 );
Lits[0] = toLitCond( Vec_IntEntry(vTopVarNums, i-1), 1 );
Lits[1] = toLitCond( pCnfPart->pVarNums[pObjPo->Id], 0 );
if ( !sat_solver_addclause( pSat, Lits, Lits+2 ) )
assert( 0 );
nClauses += 2;
}
// add CNF to the SAT solver
for ( i = 0; i < pCnfPart->nClauses; i++ )
if ( !sat_solver_addclause( pSat, pCnfPart->pClauses[i], pCnfPart->pClauses[i+1] ) )
break;
if ( i < pCnfPart->nClauses )
{
// printf( "SAT solver became UNSAT after adding clauses.\n" );
RetValue = 1;
break;
}
// create new set of POs to derive new top
Vec_PtrClear( vTop );
Vec_PtrPush( vTop, Aig_ManPo(p, 0) );
Vec_IntClear( vTopVarNums );
nOldSize = Vec_IntSize(vState);
Vec_IntFillExtra( vState, nOldSize + Aig_ManRegNum(p), -1 );
Vec_PtrForEachEntry( Aig_Obj_t *, vBot, pObjPi, i )
{
assert( Aig_ObjIsPi(pObjPi) );
if ( Saig_ObjIsLo(p, pObjPi) )
{
pObjPiCopy = (Aig_Obj_t *)pObjPi->pData;
assert( pObjPiCopy != NULL );
Vec_PtrPush( vTop, Saig_ObjLoToLi(p, pObjPi) );
Vec_IntPush( vTopVarNums, pCnfPart->pVarNums[pObjPiCopy->Id] );
iReg = pObjPi->PioNum - Saig_ManPiNum(p);
assert( iReg >= 0 && iReg < Aig_ManRegNum(p) );
Vec_IntWriteEntry( vState, nOldSize+iReg, pCnfPart->pVarNums[pObjPiCopy->Id] );
}
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Inserts the given mapping into the netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ntl_Man_t * Ntl_ManInsertMapping( Ntl_Man_t * p, Vec_Ptr_t * vMapping, Aig_Man_t * pAig )
{
char Buffer[1000];
Vec_Ptr_t * vCopies;
Vec_Int_t * vCover;
Ntl_Mod_t * pRoot;
Ntl_Obj_t * pNode;
Ntl_Net_t * pNet, * pNetCo;
Ntl_Lut_t * pLut;
int i, k, nDigits;
assert( Vec_PtrSize(p->vCis) == Aig_ManPiNum(pAig) );
assert( Vec_PtrSize(p->vCos) == Aig_ManPoNum(pAig) );
p = Ntl_ManStartFrom( p );
pRoot = Ntl_ManRootModel( p );
assert( Ntl_ModelNodeNum(pRoot) == 0 );
// map the AIG back onto the design
Ntl_ManForEachCiNet( p, pNet, i )
pNet->pCopy = Aig_ManPi( pAig, i );
// start mapping of AIG nodes into their copies
vCopies = Vec_PtrStart( Aig_ManObjNumMax(pAig) );
Ntl_ManForEachCiNet( p, pNet, i )
Vec_PtrWriteEntry( vCopies, ((Aig_Obj_t *)pNet->pCopy)->Id, pNet );
// create a new node for each LUT
vCover = Vec_IntAlloc( 1 << 16 );
nDigits = Aig_Base10Log( Vec_PtrSize(vMapping) );
Vec_PtrForEachEntry( Ntl_Lut_t *, vMapping, pLut, i )
{
pNode = Ntl_ModelCreateNode( pRoot, pLut->nFanins );
pNode->pSop = Kit_PlaFromTruth( p->pMemSops, pLut->pTruth, pLut->nFanins, vCover );
if ( !Kit_TruthIsConst0(pLut->pTruth, pLut->nFanins) && !Kit_TruthIsConst1(pLut->pTruth, pLut->nFanins) )
{
for ( k = 0; k < pLut->nFanins; k++ )
{
pNet = (Ntl_Net_t *)Vec_PtrEntry( vCopies, pLut->pFanins[k] );
if ( pNet == NULL )
{
printf( "Ntl_ManInsert(): Internal error: Net not found.\n" );
return 0;
}
Ntl_ObjSetFanin( pNode, pNet, k );
}
}
else
pNode->nFanins = 0;
sprintf( Buffer, "lut%0*d", nDigits, i );
if ( (pNet = Ntl_ModelFindNet( pRoot, Buffer )) )
{
printf( "Ntl_ManInsert(): Internal error: Intermediate net name is not unique.\n" );
return 0;
}
pNet = Ntl_ModelFindOrCreateNet( pRoot, Buffer );
if ( !Ntl_ModelSetNetDriver( pNode, pNet ) )
{
printf( "Ntl_ManInsert(): Internal error: Net has more than one fanin.\n" );
return 0;
}
Vec_PtrWriteEntry( vCopies, pLut->Id, pNet );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMfs( Abc_Ntk_t * pNtk, Mfs_Par_t * pPars )
{
extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );
Bdc_Par_t Pars = {0}, * pDecPars = &Pars;
ProgressBar * pProgress;
Mfs_Man_t * p;
Abc_Obj_t * pObj;
Vec_Vec_t * vLevels;
Vec_Ptr_t * vNodes;
int i, k, nNodes, nFaninMax, clk = clock(), clk2;
int nTotalNodesBeg = Abc_NtkNodeNum(pNtk);
int nTotalEdgesBeg = Abc_NtkGetTotalFanins(pNtk);
assert( Abc_NtkIsLogic(pNtk) );
nFaninMax = Abc_NtkGetFaninMax(pNtk);
if ( pPars->fResub )
{
if ( nFaninMax > 8 )
{
printf( "Nodes with more than %d fanins will node be processed.\n", 8 );
nFaninMax = 8;
}
}
else
{
if ( nFaninMax > MFS_FANIN_MAX )
{
printf( "Nodes with more than %d fanins will node be processed.\n", MFS_FANIN_MAX );
nFaninMax = MFS_FANIN_MAX;
}
}
// perform the network sweep
Abc_NtkSweep( pNtk, 0 );
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// start the manager
p = Mfs_ManAlloc( pPars );
p->pNtk = pNtk;
p->nFaninMax = nFaninMax;
// precomputer power-aware metrics
if ( pPars->fPower )
{
extern Vec_Int_t * Abc_NtkPowerEstimate( Abc_Ntk_t * pNtk, int fProbOne );
if ( pPars->fResub )
p->vProbs = Abc_NtkPowerEstimate( pNtk, 0 );
else
p->vProbs = Abc_NtkPowerEstimate( pNtk, 1 );
printf( "Total switching before = %7.2f.\n", Abc_NtkMfsTotalSwitching(pNtk) );
}
if ( pNtk->pExcare )
{
Abc_Ntk_t * pTemp;
if ( Abc_NtkPiNum(pNtk->pExcare) != Abc_NtkCiNum(pNtk) )
printf( "The PI count of careset (%d) and logic network (%d) differ. Careset is not used.\n",
Abc_NtkPiNum(pNtk->pExcare), Abc_NtkCiNum(pNtk) );
else
{
pTemp = Abc_NtkStrash( pNtk->pExcare, 0, 0, 0 );
p->pCare = Abc_NtkToDar( pTemp, 0, 0 );
Abc_NtkDelete( pTemp );
p->vSuppsInv = Aig_ManSupportsInverse( p->pCare );
}
}
if ( p->pCare != NULL )
printf( "Performing optimization with %d external care clauses.\n", Aig_ManPoNum(p->pCare) );
// prepare the BDC manager
if ( !pPars->fResub )
{
pDecPars->nVarsMax = (nFaninMax < 3) ? 3 : nFaninMax;
pDecPars->fVerbose = pPars->fVerbose;
p->vTruth = Vec_IntAlloc( 0 );
p->pManDec = Bdc_ManAlloc( pDecPars );
}
// label the register outputs
if ( p->pCare )
{
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pData = (void *)(PORT_PTRUINT_T)i;
}
// compute levels
Abc_NtkLevel( pNtk );
Abc_NtkStartReverseLevels( pNtk, pPars->nGrowthLevel );
// compute don't-cares for each node
nNodes = 0;
p->nTotalNodesBeg = nTotalNodesBeg;
p->nTotalEdgesBeg = nTotalEdgesBeg;
if ( pPars->fResub )
{
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( p->pPars->nDepthMax && (int)pObj->Level > p->pPars->nDepthMax )
continue;
if ( Abc_ObjFaninNum(pObj) < 2 || Abc_ObjFaninNum(pObj) > nFaninMax )
continue;
if ( !p->pPars->fVeryVerbose )
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( pPars->fResub )
Abc_NtkMfsResub( p, pObj );
else
Abc_NtkMfsNode( p, pObj );
}
Extra_ProgressBarStop( pProgress );
}
// create reverse supports
clk = clock();
vSuppsIn = Vec_VecStart( Aig_ManPiNum(p) );
Aig_ManForEachPo( p, pObj, i )
{
vSup = (Vec_Int_t *)Vec_VecEntry( vSupps, i );
Vec_IntForEachEntry( vSup, Entry, k )
Vec_VecPush( vSuppsIn, Entry, (void *)(ABC_PTRUINT_T)i );
}
ABC_PRT( "Inverse ", clock() - clk );
clk = clock();
// compute extended supports
Largest = 0;
vSuppsNew = Vec_PtrAlloc( Aig_ManPoNum(p) );
vOverNew = Vec_IntAlloc( Aig_ManPoNum(p) );
vQuantNew = Vec_IntAlloc( Aig_ManPoNum(p) );
// pProgress = Bar_ProgressStart( stdout, Aig_ManPoNum(p) );
Aig_ManForEachPo( p, pObj, i )
{
// Bar_ProgressUpdate( pProgress, i, NULL );
// get old supports
vSup = (Vec_Int_t *)Vec_VecEntry( vSupps, i );
if ( Vec_IntSize(vSup) < 2 )
continue;
// compute new supports
CountOver = CountQuant = 0;
vSupNew = Vec_IntDup( vSup );
// go through the nodes where the first var appears
Aig_ManForEachPo( p, pObj, k )
void ToCNFAIG::toCNF(const BBNodeAIG& top, Cnf_Dat_t*& cnfData,
ToSATBase::ASTNodeToSATVar& nodeToVar,
bool needAbsRef, BBNodeManagerAIG& mgr) {
assert(cnfData == NULL);
Aig_ObjCreatePo(mgr.aigMgr, top.n);
if (!needAbsRef) {
Aig_ManCleanup( mgr.aigMgr); // remove nodes not connected to the PO.
}
Aig_ManCheck( mgr.aigMgr); // check that AIG looks ok.
assert(Aig_ManPoNum(mgr.aigMgr) == 1);
// UseZeroes gives assertion errors.
// Rewriting is sometimes very slow. Can it be configured to be faster?
// What about refactoring???
int nodeCount = mgr.aigMgr->nObjs[AIG_OBJ_AND];
if (uf.stats_flag)
cerr << "Nodes before AIG rewrite:" << nodeCount << endl;
if (!needAbsRef && uf.isSet("aig-rewrite","0")) {
Dar_LibStart();
Aig_Man_t * pTemp;
Dar_RwrPar_t Pars, *pPars = &Pars;
Dar_ManDefaultRwrParams(pPars);
// Assertion errors occur with this enabled.
// pPars->fUseZeros = 1;
// For mul63bit.smt2 with iterations =3 & nCutsMax = 8
// CNF generation was taking 139 seconds, solving 10 seconds.
// With nCutsMax =2, CNF generation takes 16 seconds, solving 10 seconds.
// The rewriting doesn't remove as many nodes of course..
int iterations = 3;
for (int i = 0; i < iterations; i++) {
mgr.aigMgr = Aig_ManDup(pTemp = mgr.aigMgr, 0);
Aig_ManStop(pTemp);
Dar_ManRewrite(mgr.aigMgr, pPars);
mgr.aigMgr = Aig_ManDup(pTemp = mgr.aigMgr, 0);
Aig_ManStop(pTemp);
if (uf.stats_flag)
cerr << "After rewrite [" << i << "] nodes:"
<< mgr.aigMgr->nObjs[AIG_OBJ_AND] << endl;
if (nodeCount == mgr.aigMgr->nObjs[AIG_OBJ_AND])
break;
}
}
if (!uf.isSet("simple-cnf","0")) {
cnfData = Cnf_Derive(mgr.aigMgr, 0);
if (uf.stats_flag)
cerr << "advanced CNF" << endl;
} else {
cnfData = Cnf_DeriveSimple(mgr.aigMgr, 0);
if (uf.stats_flag)
cerr << "simple CNF" << endl;
}
BBNodeManagerAIG::SymbolToBBNode::const_iterator it;
assert(nodeToVar.size() == 0);
//todo. cf. with addvariables above...
// Each symbol maps to a vector of CNF variables.
for (it = mgr.symbolToBBNode.begin(); it != mgr.symbolToBBNode.end(); it++) {
const ASTNode& n = it->first;
const vector<BBNodeAIG> &b = it->second;
assert(nodeToVar.find(n) == nodeToVar.end());
const int width = (n.GetType() == BOOLEAN_TYPE) ? 1 : n.GetValueWidth();
// INT_MAX for parts of symbols that didn't get encoded.
vector<unsigned> v(width, ~((unsigned) 0));
for (unsigned i = 0; i < b.size(); i++) {
if (!b[i].IsNull()) {
Aig_Obj_t * pObj;
pObj = (Aig_Obj_t*) Vec_PtrEntry(mgr.aigMgr->vPis,
b[i].symbol_index);
v[i] = cnfData->pVarNums[pObj->Id];
}
}
nodeToVar.insert(make_pair(n, v));
}
assert(cnfData != NULL);
}
/**Function*************************************************************
Synopsis [Checks the consistency of the AIG manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_ManCheck( Aig_Man_t * p )
{
Aig_Obj_t * pObj, * pObj2;
int i;
// check primary inputs
Aig_ManForEachPi( p, pObj, i )
{
if ( Aig_ObjFanin0(pObj) || Aig_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The PI node \"%p\" has fanins.\n", pObj );
return 0;
}
}
// check primary outputs
Aig_ManForEachPo( p, pObj, i )
{
if ( !Aig_ObjFanin0(pObj) )
{
printf( "Aig_ManCheck: The PO node \"%p\" has NULL fanin.\n", pObj );
return 0;
}
if ( Aig_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The PO node \"%p\" has second fanin.\n", pObj );
return 0;
}
}
// check internal nodes
Aig_ManForEachObj( p, pObj, i )
{
if ( !Aig_ObjIsNode(pObj) )
continue;
if ( !Aig_ObjFanin0(pObj) || !Aig_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The AIG has internal node \"%p\" with a NULL fanin.\n", pObj );
return 0;
}
if ( Aig_ObjFanin0(pObj)->Id >= Aig_ObjFanin1(pObj)->Id )
{
printf( "Aig_ManCheck: The AIG has node \"%p\" with a wrong ordering of fanins.\n", pObj );
return 0;
}
pObj2 = Aig_TableLookup( p, pObj );
if ( pObj2 != pObj )
{
printf( "Aig_ManCheck: Node \"%p\" is not in the structural hashing table.\n", pObj );
return 0;
}
}
// count the total number of nodes
if ( Aig_ManObjNum(p) != 1 + Aig_ManPiNum(p) + Aig_ManPoNum(p) + Aig_ManBufNum(p) + Aig_ManAndNum(p) + Aig_ManExorNum(p) + Aig_ManLatchNum(p) )
{
printf( "Aig_ManCheck: The number of created nodes is wrong.\n" );
printf( "C1 = %d. Pi = %d. Po = %d. Buf = %d. And = %d. Xor = %d. Lat = %d. Total = %d.\n",
1, Aig_ManPiNum(p), Aig_ManPoNum(p), Aig_ManBufNum(p), Aig_ManAndNum(p), Aig_ManExorNum(p), Aig_ManLatchNum(p),
1 + Aig_ManPiNum(p) + Aig_ManPoNum(p) + Aig_ManBufNum(p) + Aig_ManAndNum(p) + Aig_ManExorNum(p) + Aig_ManLatchNum(p) );
printf( "Created = %d. Deleted = %d. Existing = %d.\n",
p->nCreated, p->nDeleted, p->nCreated - p->nDeleted );
return 0;
}
// count the number of nodes in the table
if ( Aig_TableCountEntries(p) != Aig_ManAndNum(p) + Aig_ManExorNum(p) + Aig_ManLatchNum(p) )
{
printf( "Aig_ManCheck: The number of nodes in the structural hashing table is wrong.\n" );
printf( "Entries = %d. And = %d. Xor = %d. Lat = %d. Total = %d.\n",
Aig_TableCountEntries(p), Aig_ManAndNum(p), Aig_ManExorNum(p), Aig_ManLatchNum(p),
Aig_ManAndNum(p) + Aig_ManExorNum(p) + Aig_ManLatchNum(p) );
return 0;
}
// if ( !Aig_ManIsAcyclic(p) )
// return 0;
return 1;
}
