void Speaker_ReveiverMode_close(void)
{
/* Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); //speaker L PGA gain control: mute // removed in MT6328 */
Ana_Set_Reg(SPK_CON2, 0x0014, 0xffff); /* Turn off OC function */
Ana_Set_Reg(SPK_ANA_CON0, 0x0, 0xffff); /* Set mute PGA gain */
Ana_Set_Reg(SPK_CON0, 0x0, 0xffff); /* set mute amp gain, amp L-ch disable */
}
void Speaker_ReveiverMode_close(void)
{
Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); //speaker L PGA gain control: mute
Ana_Set_Reg(SPK_CON2, 0x0014, 0xffff); //Turn off OC function
Ana_Set_Reg(SPK_ANA_CON0, 0x0, 0xffff); //Set mute PGA gain
Ana_Set_Reg(SPK_CON0, 0x0, 0xffff); //set mute amp gain, amp L-ch disable
}
void Ana_Recover_AudioPlayback(void)
{
kal_uint32 u4AUD_CON9 = 0;
PRINTK_ANA_REG("Ana_Recover_AudioPlayback\n");
u4AUD_CON9 = Ana_Get_Backup_Memory(AUDIO_CON9);
Ana_Recover_Reg(AUDIO_NCP0);
Ana_Recover_Reg(AUDIO_NCP1);
Ana_Recover_Reg(AUDIO_LDO0);
Ana_Recover_Reg(AUDIO_LDO1);
Ana_Recover_Reg(AUDIO_LDO2);
Ana_Recover_Reg(AUDIO_GLB0);
Ana_Recover_Reg(AUDIO_GLB1);
Ana_Recover_Reg(AUDIO_REG1);
Ana_Recover_Reg(AUDIO_CON0);//set line-in gain and select ZCD source
Ana_Recover_Reg(AUDIO_CON1);
Ana_Recover_Reg(AUDIO_CON2);
Ana_Recover_Reg(AUDIO_CON3);
Ana_Recover_Reg(AUDIO_CON5);
Ana_Recover_Reg(AUDIO_CON6);
Ana_Recover_Reg(AUDIO_CON7);
Ana_Recover_Reg(AUDIO_CON8);
if(u4AUD_CON9&0x01) //Follow audio fifo control flow
{
Ana_Set_Reg(AUDIO_CON9, u4AUD_CON9, 0xfffffffe);
Ana_Set_Reg(AUDIO_CON9, u4AUD_CON9, 0x00000001);
}
else
{
Ana_Recover_Reg(AUDIO_CON9);
}
Ana_Recover_Reg(AUDIO_CON10);
Ana_Recover_Reg(AUDIO_CON14);
Ana_Recover_Reg(AUDIO_CON17);
}
void Speaker_ClassAB_close(void)
{
pr_warn("%s\n", __func__);
Ana_Set_Reg(SPK_CON9, 0x2100, 0xffff); /* Set Vcm high PSRR mode */
Ana_Set_Reg(SPK_ANA_CON0, 0x0800, 0xffff); /* Set 0dB PGA gain(level when trimming) */
Ana_Set_Reg(SPK_CON0, 0x1005, 0xffff); /* set -6dB amp gain(level when trimming) */
Ana_Set_Reg(SPK_CON0, 0x1004, 0xffff); /* amp L-ch disable */
}
void Speaker_ClassD_close(void)
{
printk("%s\n", __func__);
Ana_Set_Reg(SPK_CON9, 0x2A00, 0xffff); //Set Vcm high PSRR mode
Ana_Set_Reg(SPK_ANA_CON0, 0x5000, 0xffff); //Set 12dB PGA gain(level when trimming)
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); //set 0dB amp gain(level when trimming)
Ana_Set_Reg(SPK_CON0, 0x3000, 0xffff); //amp L-ch disable
}
void Speaker_ReveiverMode_Open(void)
{
pr_warn("%s\n", __func__);
Ana_Set_Reg(SPK_CON0, 0x1304, 0xffff);
/* Enable thermal_shout_down, OC_shout_down. Set class AB mode, -6dB amp gain */
Ana_Set_Reg(SPK_CON2, 0x02A4, 0xffff); /* Turn on OC function, set SPK PGA in DCC mode */
/* Ana_Set_Reg(SPK_CON9, 0x2100, 0xffff); //Set Fast Vcm mode // removed in MT6328 */
Ana_Set_Reg(SPK_ANA_CON0, 0x2000, 0xffff); /* Set 6dB PGA gain */
Ana_Set_Reg(SPK_CON0, 0x1305, 0xffff); /* Turn on speaker */
udelay(2000);
/* Ana_Set_Reg(SPK_CON9, 0x0100, 0xffff); //Set Vcm high PSRR mode // removed in MT6328 */
}
static int mtk_voice1_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtimeStream = substream->runtime;
pr_warn("mtk_voice1_prepare rate = %d channels = %d period_size = %lu\n",
runtimeStream->rate, runtimeStream->channels, runtimeStream->period_size);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
pr_warn("%s with SNDRV_PCM_STREAM_CAPTURE\n", __func__);
return 0;
}
/* here start digital part */
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03,
Soc_Aud_InterConnectionOutput_O17);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04,
Soc_Aud_InterConnectionOutput_O18);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14,
Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14,
Soc_Aud_InterConnectionOutput_O04);
/* start I2S DAC out */
SetI2SDacOut(substream->runtime->rate, false, Soc_Aud_I2S_WLEN_WLEN_16BITS);
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
ConfigAdcI2S(substream);
SetI2SAdcIn(&mAudioDigitalI2S);
SetI2SDacEnable(true);
#ifdef PMIC_RESET_WORKAROUND
pr_warn("%s ,PMIC_RESET_WORKAROUND reset ABB_AFE_CON2/ABB_AFE_CON4\n", __func__);
Ana_Set_Reg(ABB_AFE_CON2, 0x0, 0xffff); /* reset to default value */
Ana_Set_Reg(ABB_AFE_CON4, 0x0, 0xffff); /* reset to default value */
#endif
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
EnableAfe(true);
Voice1Pcm.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ?
Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K;
Voice1Pcm.mAsyncFifoSel = Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO;
SetModemPcmConfig(MODEM_1, Voice1Pcm);
SetModemPcmEnable(MODEM_1, true);
Voice_Status = true;
return 0;
}
static int mtk_pcm_I2S0dl1_start(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
printk("%s\n", __func__);
// here start digital part
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O00);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O01);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O03);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O04);
SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true);
SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate);
SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels);
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
EnableAfe(true);
#ifdef _DEBUG_6328_CLK
//Debug 6328 Digital to Analog path clock and data work or not. and read TEST_OUT(0x206)
// Ana_Set_Reg(AFE_MON_DEBUG0, 0x4600 , 0xcf00); // monitor 6328 digitala data sent to analog or not
Ana_Set_Reg(AFE_MON_DEBUG0, 0x4200 , 0xcf00); // monitor 6328 digitala data sent to analog or not
Ana_Set_Reg(TEST_CON0, 0x0e00 , 0xffff);
#endif
#if 0 // test 6328 sgen
Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffff);
Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff);
Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
// Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0002, 0x0002); //UL from sinetable
Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0001, 0x0001); //DL from sinetable
#endif
return 0;
}
bool GetSpeakerOcFlag(void)
{
unsigned int OCregister = 0;
unsigned int bitmask = 1;
bool DmodeFlag = false;
bool ABmodeFlag = false;
Ana_Set_Reg(TOP_CKPDN_CON2_CLR, 0x3, 0xffff);
OCregister = Ana_Get_Reg(SPK_CON6);
DmodeFlag = OCregister & (bitmask << 14); // ; no.14 bit is SPK_D_OC_L_DEG
ABmodeFlag = OCregister & (bitmask << 15); // ; no.15 bit is SPK_AB_OC_L_DEG
printk("OCregister = %d \n", OCregister);
return (DmodeFlag | ABmodeFlag);
}
void Speaker_ReveiverMode_Open(void)
{
printk("%s\n", __func__);
Ana_Set_Reg(SPK_CON0, 0x1304, 0xffff); //Enable thermal_shout_down, OC_shout_down. Set class AB mode, -6dB amp gain
Ana_Set_Reg(SPK_CON2, 0x02A4, 0xffff); //Turn on OC function, set SPK PGA in DCC mode
Ana_Set_Reg(SPK_CON9, 0x2100, 0xffff); //Set Fast Vcm mode
Ana_Set_Reg(SPK_ANA_CON0, 0x2000, 0xffff); //Set 6dB PGA gain
Ana_Set_Reg(SPK_CON0, 0x1305, 0xffff); //Turn on speaker
udelay(2000);
Ana_Set_Reg(SPK_CON9, 0x0100, 0xffff); //Set Vcm high PSRR mode
}
void Speaker_ClassD_Open(void)
{
kal_uint32 i, SPKTrimReg = 0;
pr_warn("%s\n", __func__);
/* spk trim */
Ana_Set_Reg(SPK_CON7, 0x4531, 0xffff); /* TD1,TD2,TD3 for trim (related with trim waiting time) */
Ana_Set_Reg(SPK_CON0, 0x3008, 0xffff); /* Set to class D mode, set 0dB amplifier gain, enable trim function */
Ana_Set_Reg(SPK_CON13, 0x1800, 0xffff); /* Offset trim RSV bit */
Ana_Set_Reg(SPK_CON2, 0x04A4, 0xffff); /* Turn on OC function, set SPK PGA in DCC mod */
Ana_Set_Reg(SPK_ANA_CON0, 0x5000, 0xffff); /* Set 12dB PGA gain */
Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); /* Set Fast Vcm mode */
Ana_Set_Reg(SPK_CON0, 0x3009, 0xffff); /* Turn on speaker */
Ana_Set_Reg(SPK_CON9, 0x0A00, 0xffff); /* Set Vcm high PSRR mode */
for (i = 0; i < 10; i++)
udelay(1000); /* wait 10ms for trimming */
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); /* Turn off trim,(set to class D mode) */
Ana_Set_Reg(SPK_CON13, 0x0000, 0xffff); /* Clock from Saw-tooth to Triangular wave */
SPKTrimReg = Ana_Get_Reg(SPK_CON1);
if ((SPKTrimReg & 0x8000) == 0)
pr_warn("spk trim fail!\n");
else
pr_warn("spk trim offset=%d\n", (SPKTrimReg & 0x1f));
/* spk amp gain fixed at 0dB */
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); /* set 0dB amplifier gain */
}
static void StartAudioCaptureHardware(struct snd_pcm_substream *substream)
{
printk("StartAudioCaptureHardware \n");
ConfigAdcI2S(substream);
SetI2SAdcIn(mAudioDigitalI2S);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_16_BIT);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O10);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC) == false)
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
SetI2SAdcEnable(true);
}
else
{
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, true);
}
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O09);
SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O10);
if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE || substream->runtime->format == SNDRV_PCM_FORMAT_U32_LE)
{
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_VUL, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O09);
SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O10);
}
// here to set interrupt
SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);
SetSampleRate(Soc_Aud_Digital_Block_MEM_VUL, substream->runtime->rate);
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL, true);
EnableAfe(true);
#ifdef DENALI_FPGA_EARLYPORTING //ccc early porting test, copy from TurnOnADcPowerACC()
//here to set digital part
//Topck_Enable(true);
//AdcClockEnable(true);
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk //early porting 6752 remove
Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON1_L, 0x0000, 0xffff); //power on ADC clk //early porting 6752 remove
Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
Ana_Set_Reg(AFE_UL_DL_CON0, 0x0001, 0xffff); //turn on afe
Ana_Set_Reg(AFE_PMIC_NEWIF_CFG2, 0x302F, 0xffff); // config UL up8x_rxif adc voice mode, 8k sample rate
Ana_Set_Reg(AFE_UL_SRC0_CON0_H, (0 << 3 | 0 << 1) , 0x001f);// ULsampling rate, 8k sample rate
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_H, (ULSampleRateTransform(SampleRate_VUL2) << 3 | ULSampleRateTransform(SampleRate_VUL2) << 1) , 0x001f); // ULsampling rate
//Ana_Set_Reg(AFE_ADDA2_UL_SRC_CON0_L, 0x0041, 0xffff);
Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0005, 0xffff); //power on uplink, and loopback to DL
Afe_Set_Reg(FPGA_CFG1, 0x1, 0xffff); // must set in FPGA platform for PMIC digital loopback
#endif
}
static ssize_t mt_soc_debug_write(struct file *f, const char __user *buf,
size_t count, loff_t *offset)
{
int ret = 0;
char InputString[256];
char *token1 = NULL ;
char *token2 = NULL ;
char *token3 = NULL;
char *token4 = NULL;
char *token5 = NULL;
char *temp = NULL;
long unsigned int regaddr = 0;
long unsigned int regvalue = 0;
char delim[] = " ,";
memset((void *)InputString, 0, 256);
if (copy_from_user((InputString), buf, count))
{
printk("copy_from_user mt_soc_debug_write count = %zu temp = %s\n", count, InputString);
}
temp = kstrdup(InputString, GFP_KERNEL);
printk("copy_from_user mt_soc_debug_write count = %zu temp = %s pointer = %p\n", count, InputString, InputString);
token1 = strsep(&temp, delim);
printk("token1 \n");
printk("token1 = %s\n", token1);
token2 = strsep(&temp, delim);
printk("token2 = %s\n", token2);
token3 = strsep(&temp, delim);
printk("token3 = %s\n", token3);
token4 = strsep(&temp, delim);
printk("token4 = %s\n", token4);
token5 = strsep(&temp, delim);
printk("token5 = %s\n", token5);
if (strcmp(token1, ParSetkeyAfe) == 0)
{
printk("strcmp (token1,ParSetkeyAfe) \n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAfe, regaddr, regvalue);
Afe_Set_Reg(regaddr, regvalue, 0xffffffff);
regvalue = Afe_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAfe, regaddr, regvalue);
}
if (strcmp(token1, ParSetkeyAna) == 0)
{
printk("strcmp (token1,ParSetkeyAna)\n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAna, regaddr, regvalue);
//clk_buf_ctrl(CLK_BUF_AUDIO, true); //k2 need?
AudDrv_Clk_On();
audckbufEnable(true);
Ana_Set_Reg(regaddr, regvalue, 0xffffffff);
regvalue = Ana_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyAna, regaddr, regvalue);
}
if (strcmp(token1, ParSetkeyCfg) == 0)
{
printk("strcmp (token1,ParSetkeyCfg)\n");
ret = strict_strtoul(token3, 16, ®addr);
ret = strict_strtoul(token5, 16, ®value);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyCfg, regaddr, regvalue);
SetClkCfg(regaddr, regvalue, 0xffffffff);
regvalue = GetClkCfg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", ParSetkeyCfg, regaddr, regvalue);
}
if (strcmp(token1, PareGetkeyAfe) == 0)
{
printk("strcmp (token1,PareGetkeyAfe)\n");
ret = strict_strtoul(token3, 16, ®addr);
regvalue = Afe_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", PareGetkeyAfe, regaddr, regvalue);
}
if (strcmp(token1, PareGetkeyAna) == 0)
{
printk("strcmp (token1,PareGetkeyAna)\n");
ret = strict_strtoul(token3, 16, ®addr);
regvalue = Ana_Get_Reg(regaddr);
printk("%s regaddr = 0x%lu regvalue = 0x%lu\n", PareGetkeyAna, regaddr, regvalue);
}
return count;
}
void Speaker_ClassD_Open(void)
{
kal_uint32 i, SPKTrimReg = 0;
printk("%s\n", __func__);
// spk trim
Ana_Set_Reg(SPK_CON7, 0x4531, 0xffff); //TD1,TD2,TD3 for trim (related with trim waiting time)
Ana_Set_Reg(SPK_CON0, 0x3008, 0xffff);//Set to class D mode, set 0dB amplifier gain, enable trim function
Ana_Set_Reg(SPK_CON13, 0x1800, 0xffff);//Offset trim RSV bit
Ana_Set_Reg(SPK_CON2, 0x04A4, 0xffff); //Turn on OC function, set SPK PGA in DCC mod
Ana_Set_Reg(SPK_ANA_CON0, 0x5000, 0xffff); //Set 12dB PGA gain
Ana_Set_Reg(SPK_CON9, 0x2000, 0xffff); //Set Fast Vcm mode
Ana_Set_Reg(SPK_CON0, 0x3009, 0xffff); //Turn on speaker
Ana_Set_Reg(SPK_CON9, 0x0A00, 0xffff); //Set Vcm high PSRR mode
for (i = 0; i < 10; i++)
{
udelay(1000); //wait 10ms for trimming
}
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); //Turn off trim,(set to class D mode)
Ana_Set_Reg(SPK_CON13, 0x0000, 0xffff); //Clock from Saw-tooth to Triangular wave
SPKTrimReg = Ana_Get_Reg(SPK_CON1);
if ((SPKTrimReg & 0x8000) == 0)
{
printk("spk trim fail!\n");
}
else
{
printk("spk trim offset=%d\n", (SPKTrimReg & 0x1f));
}
// spk amp gain fixed at 0dB
Ana_Set_Reg(SPK_CON0, 0x3001, 0xffff); //set 0dB amplifier gain
}
void Ana_Recover_Reg(kal_uint32 offset)
{
kal_uint32 value = 0;
value = Ana_Get_Backup_Memory(offset);
Ana_Set_Reg(offset, value, 0xffffffff);
}
