/** Call before jumping to Normal World This function allows the firmware platform to do extra actions before jumping to the Normal World **/ VOID ArmPlatformSecExtraAction ( IN UINTN MpId, OUT UINTN* JumpAddress ) { CHAR8 Buffer[100]; UINTN CharCount; if (FeaturePcdGet (PcdStandalone) == FALSE) { // // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib // if (IS_PRIMARY_CORE(MpId)) { UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress); // Patch the DRAM to make an infinite loop at the start address *StartAddress = 0xEAFFFFFE; // opcode for while(1) CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress); SerialPortWrite ((UINT8 *) Buffer, CharCount); *JumpAddress = PcdGet32(PcdFvBaseAddress); } else { // When the primary core is stopped by the hardware debugger to copy the firmware // into DRAM. The secondary cores are still running. As soon as the first bytes of // the firmware are written into DRAM, the secondary cores will start to execute the // code even if the firmware is not entirely written into the memory. // That's why the secondary cores need to be parked in WFI and wake up once the // firmware is ready. *JumpAddress = (UINTN)NonSecureWaitForFirmware; } } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { // // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib // if (IS_PRIMARY_CORE(MpId)) { // Signal the secondary cores they can jump to PEI phase ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId)); // To enter into Non Secure state, we need to make a return from exception *JumpAddress = PcdGet32(PcdFvBaseAddress); } else { // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary // cores would make crash the system by setting their stacks in DRAM before the primary core has not // finished to initialize the system memory. *JumpAddress = (UINTN)NonSecureWaitForFirmware; } } else { *JumpAddress = PcdGet32(PcdFvBaseAddress); } }
VOID EFIAPI PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { EFI_SEC_PEI_HAND_OFF SecCoreData; UINTN PpiListSize; EFI_PEI_PPI_DESCRIPTOR *PpiList; UINTN TemporaryRamBase; UINTN TemporaryRamSize; CreatePpiList (&PpiListSize, &PpiList); // Enable the GIC Distributor ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase)); // If ArmVe has not been built as Standalone then we need to wake up the secondary cores if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) { // Sending SGI to all the Secondary CPU interfaces ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); } // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at // the base of the primary core stack PpiListSize = ALIGN_VALUE(PpiListSize, 0x4); TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize; TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned // to ensure the stack pointer is 4-byte aligned. TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1)); // // Bind this information into the SEC hand-off state // Note: this must be in sync with the stuff in the asm file // Note also: HOBs (pei temp ram) MUST be above stack // SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress); SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamSize = TemporaryRamSize; SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; SecCoreData.StackBase = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4); SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase; // Jump to PEI core entry point (PeiCoreEntryPoint)(&SecCoreData, PpiList); }