////////////////////////////////////////////////////////////////////////////////
//! See hw_lradc.h for details.
////////////////////////////////////////////////////////////////////////////////
void hw_lradc_ConfigureChannel( hw_lradc_Channel_t eChannel,
bool bEnableDivideByTwo,
bool bEnableAccum,
uint8_t u8NumSamples)
{
// Set the analog divide-by two function
if(bEnableDivideByTwo)
{
// Enable the divide-by-two of a LRADC channel
BF_SETV(LRADC_CTRL2, DIVIDE_BY_TWO, (1 << eChannel));
}
else
{
// Disable the divide-by-two of a LRADC channel
BF_CLRV(LRADC_CTRL2, DIVIDE_BY_TWO, (1 << eChannel));
}
// Clear the accumulator & NUM_SAMPLES
HW_LRADC_CHn_CLR(eChannel, 0xFFFFFFFF);
// Sets NUM_SAMPLES bitfield of HW_LRADC_CHn register.
BF_WRn(LRADC_CHn, eChannel, NUM_SAMPLES, (u8NumSamples & 0x1f));
// Set ACCUMULATE bit of HW_LRADC_CHn register
if(bEnableAccum)
{
// Enable the accumulation of a LRADC channel
BF_SETn(LRADC_CHn, eChannel, ACCUMULATE);
}
else
{
// Disable the accumulation of a LRADC channel
BF_CLRn(LRADC_CHn, eChannel, ACCUMULATE);
}
}
static inline int __attribute__((always_inline)) read_lradc(int src)
{
BF_CLR(LRADC_CTRL1, LRADCx_IRQ(src));
BF_SETV(LRADC_CTRL0, SCHEDULE, 1 << src);
while(!BF_RD(LRADC_CTRL1, LRADCx_IRQ(src)));
return BF_RDn(LRADC_CHn, src, VALUE);
}
/* only works for channels <=7, always divide by 2, never accumulates */
static inline void __attribute__((always_inline)) setup_lradc(int src)
{
BF_CLR(LRADC_CTRL0, SFTRST);
BF_CLR(LRADC_CTRL0, CLKGATE);
/* don't bother changing the source, we are early enough at boot so that
* channel x is mapped to source x */
HW_LRADC_CHn_CLR(src) = BM_OR2(LRADC_CHn, NUM_SAMPLES, ACCUMULATE);
BF_SETV(LRADC_CTRL2, DIVIDE_BY_TWO, 1 << src);
}
void imx233_powermgmt_init(void)
{
imx233_power_set_charge_current(IMX233_CHARGE_CURRENT);
imx233_power_set_stop_current(IMX233_STOP_CURRENT);
/* assume that adc_init was called and battery monitoring via LRADC setup */
BF_WR(POWER_BATTMONITOR, EN_BATADJ, 1);
#if IMX233_SUBTARGET >= 3700
/* setup linear regulator offsets to 25 mV below to prevent contention between
* linear regulators and DCDC */
BF_WR(POWER_VDDDCTRL, LINREG_OFFSET, 2);
BF_WR(POWER_VDDACTRL, LINREG_OFFSET, 2);
BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET, 2);
/* enable DCDC (more efficient) */
BF_SET(POWER_5VCTRL, ENABLE_DCDC);
BF_CLR(POWER_5VCTRL, DCDC_XFER);
#else
BF_SET(POWER_5VCTRL, LINREG_OFFSET);
BF_SET(POWER_5VCTRL, EN_DCDC1);
BF_SET(POWER_5VCTRL, EN_DCDC2);
#endif
#if IMX233_SUBTARGET >= 3780
/* enable a few bits controlling the DC-DC as recommended by Freescale */
BF_SET(POWER_LOOPCTRL, TOGGLE_DIF);
BF_SET(POWER_LOOPCTRL, EN_CM_HYST);
BF_CLR(POWER_LOOPCTRL, EN_RCSCALE);
BF_SETV(POWER_LOOPCTRL, EN_RCSCALE, 1);
/* adjust arbitration between 4.2 and battery */
BF_WR(POWER_DCDC4P2, CMPTRIP, 0); /* 85% */
BF_WR(POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */
/* make sure we are in a known state: disable charger and 4p2 */
BF_SET(POWER_CHARGE, PWD_BATTCHRG);
BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0);
BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0);
BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2);
#endif
}
////////////////////////////////////////////////////////////////////////////////
//! See hw_lradc.h for details.
////////////////////////////////////////////////////////////////////////////////
void hw_lradc_ScheduleChannel(hw_lradc_Channel_t eChannel) // one channel only
{
// Set the SCHEDULE bitfield of HW_LRADC_CTRL0 register
BF_SETV(LRADC_CTRL0, SCHEDULE, (1 << eChannel));
}