/** Configure 16 bit timer to trigger an ISR every second
*
* Configure "measurement in progress toggle LED-signal"
*/
void timer1_init(const uint16_t timer1_value)
{
orig_timer1_count = timer1_value;
timer1_count = timer1_value;
/** Safeguard: We cannot handle 0 or 1 count measurements. */
if (orig_timer1_count <= 1) {
send_text_P(PSTR("Unsupported timer value <= 1"));
wdt_soft_reset();
}
/* Compare match value into output compare reg. A */
OCR1A = TIMER1_COMPARE_MATCH_VAL;
/* Configure and start timer */
TCCR1A =
BITF(TIMER1_COMA_MODE, COM1A, 0) |
BITF(TIMER1_COMA_MODE, COM1A, 1) |
BITF(TIMER1_WGM_MODE, WGM1, 0) |
BITF(TIMER1_WGM_MODE, WGM1, 1);
TCCR1B =
BITF(TIMER1_PRESCALER, CS1, 0) |
BITF(TIMER1_PRESCALER, CS1, 1) |
BITF(TIMER1_PRESCALER, CS1, 2) |
BITF(TIMER1_WGM_MODE, WGM1, 2) |
BITF(TIMER1_WGM_MODE, WGM1, 3);
/* output compare match A interrupt enable */
TIMSK1 |= _BV(OCIE1A);
}
/** Set up timer2 for wave generator and timer0 for gating signal
*/
INIT_FUNCTION(init7, beep_init_and_start)
{
/** configure square wave generator (timer2)
*/
/** reset current timer counter value */
TCNT2 = 0;
/** output compare A value */
OCR2A = TIMER2_COMPA_VALUE;
/** we do not use timer2's asynchronous mode */
ASSR = 0;
/** set up timer2 mode, and start it with appropriate prescale value */
TCCR2A = (BITF(TIMER2_WGM_VALUE, WGM2, 0) |
BITF(TIMER2_WGM_VALUE, WGM2, 1));
TCCR2B = BITF(TIMER2_WGM_VALUE, WGM2, 2);
/** map square wave generator (timer2) to output pin PD7 (21) (toggle pin on CTC) */
TCCR2A |= _BV(COM2A0);
/** configure gating signal (timer0)
*/
/** reset current timer counter value */
TCNT0 = TIMER0_INIT_VALUE;
/** set up timer0 mode, and start it with appropriate prescale value */
TCCR0A = (BITF(TIMER0_WGM_VALUE, WGM0, 0) |
BITF(TIMER0_WGM_VALUE, WGM0, 1));
TCCR0B = BITF(TIMER0_WGM_VALUE, WGM0, 2);
/** OVF interrupt enable on timer0 */
TIMSK0 = _BV(TOIE0);
}
inline static
void timer0_2_stop_and_reset(void)
{
/* stop gating signal (timer0) */
TCCR0B &=~ (BITF(TIMER0_CLOCK_PRESCALER_SELECT, CS0, 2) |
BITF(TIMER0_CLOCK_PRESCALER_SELECT, CS0, 1) |
BITF(TIMER0_CLOCK_PRESCALER_SELECT, CS0, 0));
/* reset timer value */
TCNT0 = TIMER0_INIT_VALUE;
/* switch off square wave generator (timer2) */
TCCR2B &=~ (BITF(TIMER2_CLOCK_PRESCALER_SELECT, CS2, 2) |
BITF(TIMER2_CLOCK_PRESCALER_SELECT, CS2, 1) |
BITF(TIMER2_CLOCK_PRESCALER_SELECT, CS2, 0));
}
BIT(IEN), /* Interrupt Enable */
#define CSR_V_IEN 6
#define CSR_IEN (1<<CSR_V_IEN)
BIT(CUR), /* Cursor active */
#define CSR_V_CUR 7
#define CSR_CUR (1<<CSR_V_CUR)
BIT(MSA), /* Mouse Button A */
#define CSR_V_MSA 8
#define CSR_MSA (1<<CSR_V_MSA)
BIT(MSA), /* Mouse Button B */
#define CSR_V_MSB 9
#define CSR_MSB (1<<CSR_V_MSB)
BIT(MSA), /* Mouse Button C */
#define CSR_V_MSC 10
#define CSR_MSC (1<<CSR_V_MSC)
BITF(MA,8), /* Memory Bank Switch (Base Address) */
#define CSR_V_MA 11
#define CSR_S_MA 4
#define CSR_M_MA (((1<<CSR_S_MA)-1)<<CSR_V_MA)
BITNCF(1), /* unused */
ENDBITS
};
#define CSR_RW (CSR_IEN|CSR_TST|CSR_VRB|CSR_FNC|CSR_VID)
/* ICSR - interrupt controller command/status register */
BITFIELD vc_icsr_bits[] = {
BITF(IRRVEC,3), /* IRR Vector */
#define ICSR_V_IRRVEC 0
#define ICSR_S_IRRVEC 3
#define ICSR_M_IRRVEC (((1<<ICSR_S_IRRVEC)-1)<<ICSR_V_IRRVEC)
#define MISC_BOOT 0x2 /* reboot */
#define MISC_CLWS 0x3 /* clear warm start */
#define MISC_CLCS 0x4 /* clear cold start */
#define TXDB_SEL (TXDB_M_SEL << TXDB_V_SEL) /* non-terminal */
#define TXDB_GETSEL(x) (((x) >> TXDB_V_SEL) & TXDB_M_SEL)
static BITFIELD rx_csr_bits[] = {
BITNCF(6), /* unused */
BIT(IE), /* Interrupt Enable */
BIT(DONE), /* Xmit Ready */
BITNCF(8), /* unused */
ENDBITS
};
static BITFIELD rx_buf_bits[] = {
BITF(DAT,8), /* data buffer */
BITNCF(5), /* unused */
BIT(RBRK),
BIT(OVR),
BIT(ERR),
ENDBITS
};
static BITFIELD tx_csr_bits[] = {
BIT(XBR), /* Break */
BITNC, /* unused */
BIT(MAINT), /* Maint */
BITNCF(3), /* unused */
BIT(IE), /* Interrupt Enable */
BIT(DONE), /* Xmit Ready */
BITNCF(8), /* unused */
#define WTC_CSRB_SQWE 0x08 /* square wave enable (Not Used by VMS) */
#define WTC_CSRB_WR (WTC_CSRB_DSE | WTC_CSRB_2412 | WTC_CSRB_DM | WTC_CSRB_SET)
const char *wtc_dse_modes[] = {"Disabled", "Enabled"};
const char *wtc_hr_modes[] = {"12Hr", "24Hr"};
const char *wtc_data_modes[] = {"BCD", "Binary"};
BITFIELD wtc_csrb_bits[] = {
BITFNAM(DST,1,wtc_dse_modes), /* Daylight Savings Time Enable */
BITFNAM(24HR,1,wtc_hr_modes), /* 24/12 Hour Mode */
BITFNAM(DM,1,wtc_data_modes), /* Data Mode */
BITNCF(4), /* Unused SQWE, UIE, AIE, PIE */
BIT(SET), /* Set In Progress */
ENDBITS
};
BITFIELD wtc_csrc_bits[] = {
BITF(VALUE,8), /* Should be unused */
ENDBITS
};
#define WTC_CSRD_VRT 0x80 /* valid time */
#define WTC_CSRD_RD (WTC_CSRD_VRT)
#define WTC_CSRD_WR (WTC_CSRD_VRT)
BITFIELD wtc_csrd_bits[] = {
BITNCF(7),
BIT(VALID), /* Valid RAM and Time (VRT) */
ENDBITS
};
BITFIELD wtc_value_bits[] = {
BITFFMT(VALUE,8,%d), /* Decimal Value */
ENDBITS
};
#define MBA_EXTDRV(x) (((x) >> MBA_V_DRV) & MBA_M_DRV)
#define MBA_EXTOFS(x) (((x) >> MBA_V_DEVOFS) & MBA_M_DEVOFS)
char *mba_regnames[] = {"CNF", "CR", "SR", "VA", "BC", "DR", "SMR", "CMD"};
/* Massbus configuration register */
#define MBACNF_OF 0x0
#define MBACNF_ADPDN 0x00800000 /* adap pdn - ni */
#define MBACNF_ADPUP 0x00400000 /* adap pup - ni */
#define MBACNF_CODE 0x00000020
#define MBACNF_RD (SBI_FAULTS|MBACNF_W1C)
#define MBACNF_W1C 0x00C00000
BITFIELD mba_cnf_bits[] = {
BITF(CODE,8), /* Adapter Code */
BITNCF(13), /* 08:20 Reserved */
BIT(OT), /* Over Temperature */
BIT(PU), /* Power Up */
BIT(PD), /* Power Down */
BITNCF(2), /* 24:25 Reserved */
BIT(XMTFLT), /* Transmit Fault */
BIT(MT), /* Multiple Transmitter */
BITNCF(1), /* 28 Reserved */
BIT(URD), /* Unexpected Read Data */
BIT(WS), /* Write Data Sequence (Fault B) */
BIT(PE), /* SBI Parity Error */
ENDBITS
};
/* Control register */
