/* open() and close() essentially control the SPI's CS pin.
* there're the followin conditions you should use open() before you transmit
* a byte through SPI:
* - you want to select a specific device connect to SPI. you can choose the
* device through parameter "devid" in spi_open()
* - you want to adjust the detail timling when you try to sent multi-byte streams.
* open() will prepare the SPI for transmitting multi-byte stream.
*
* @attention
* you should call spi_configure() before spi_open() and spi_read/write()
*
* @obsolete
* spi_open() and spi_close() originally known as spi_enable() and spi_disable()
* in module "cc2420rf"
*/
void spi_open( TiSpiAdapter * spi, uint8 devid )
{
uint16 i = 0;
// @TODO
// you should distinguish SPI0 and SPI1
#ifdef CONFIG_TARGET_OPENNODE_10
IO1CLR = BM(CSN);
#endif
#ifdef CONFIG_TARGET_OPENNODE_20
IO1CLR = BM(CSN);
#endif
#ifdef CONFIG_TARGET_OPENNODE_30
IO1CLR = BM(CSN);
#endif
#ifdef CONFIG_TARGET_WLSMODEM_11
IO0CLR = BM(CSN);
#endif
#ifdef CONFIG_TARGET_DEFAULT
IO1CLR = BM(CSN);
#endif
// the delay is to construct enough setup time of csn
// attention the delay time not to be optimized to 0
//
// @TODO you should use hal_delay here
//#pragma optimize=none
while(i < 500)
i++;
}
/**********************************************************
* start timer
* (start atmega 128 Timer/Counter)
*/
void wd_timer_start()
{
nrk_int_disable();
periodic_time_offset = 0;
logical_time = 0;
alarm_time = 0;
alarm_type = 0;
is_alarm_set = false;
is_periodic_enabled = false;
#if USE_TIMER_COUNTER == 1
TCCR1A = 0; // Compare Output Mode : Normal
TCNT1 = 0; // reset timer value
TIFR&=~BM(OCF1A); // clear OCF flag
TIMSK|=BM(OCIE1A); // enable compare interrupt
OCR1A = (uint16_t)(WD_CLOCK_TICKS); // set compare value
TCCR1B = TIMER_CLK_DIV1; // set timer scale
TCCR1B |= BM(WGM12); // Waveform Generation Mode: Clear Timer on Compare
#elif USE_TIMER_COUNTER == 3
TCCR3A = 0; // Compare Output Mode : Normal
TCNT3 = 0; // reset timer value
ETIFR&=~BM(OCF3A); // clear OCF flag
ETIMSK|=BM(OCIE3A); // enable compare interrupt
OCR3A = (uint16_t)(WD_CLOCK_TICKS); // set compare value
TCCR3B = TCLK_CPU_DIV; // set timer scale
TCCR3B |= BM(WGM32); // Waveform Generation Mode: Clear Timer on Compare
#else
#error "Must define USE_TIMER_COUNTER in wd_timer.h as 1 or 3."
#endif
nrk_int_enable();
}
void spi_close( TiSpiAdapter * spi )
{
uint16 i = 0;
// the delay is to provide enough holdup time of csn
// attention the delay time not to be optimized to 0
// @TODO
while(i < 1500)
i++;
#ifdef CONFIG_TARGET_OPENNODE_10
IO1SET = BM(CSN);
#endif
#ifdef CONFIG_TARGET_OPENNODE_20
IO1SET = BM(CSN);
#endif
#ifdef CONFIG_TARGET_OPENNODE_30
IO1SET = BM(CSN);
#endif
#ifdef CONFIG_TARGET_WLSMODEM_11
IO0SET = BM(CSN);
#endif
#ifdef CONFIG_TARGET_DEFAULT
IO1SET = BM(CSN);
#endif
}
inline void _tdma_timer5_setup()
{
TCCR5A=0;
TCCR5B=BM(CS10); // clk I/O no prescale
TCNT5=0; // 16 bit
GTCCR |= BM(PSRASY); // reset prescaler
GTCCR |= BM(PSRSYNC); // reset prescaler
}
Vect BMotion(int N)
{
Vect BM(N);
BM(0)=0.;
for ( int i = 1; i < N; ++i ){
BM(i) = BM(i-1) + Gaussian( 0., 1.);
}
return BM;
}
void LPC_TIMER0_INIT()
{
T0PR = 0; // 预分频器 有待调整
T0CCR |= BM(CAP2RE) | BM(CAP2I); //cap0.2 上升沿捕获，并产生中断
T0MCR |= BM(MR0I) | BM(MR0R) | BM(MR1I); //BM(MR2I)| BM(MR2R); //??
T0TC = 0;
VICIntSelect = 0x00000000; // 设置所有的通道为IRQ中断
VICVectCntl0 = 0x20 | 4; // Timer0分配到IRQ slot0，即最高优先级
VICVectAddr0 = (uint32)Timer0_Int; // 设置Timer1向量地址
}
void SET_VREG_INACTIVE( void )
{
#if VREG_EN_PORT == 0
IO0CLR = BM(VREG_EN);
#endif
#if VREG_EN_PORT == 1
IO1CLR = BM(VREG_EN);
#endif
}
void SET_RESET_ACTIVE( void )
{
#if RESET_N_PORT == 0
IO0CLR = BM(RESET_N);
#endif
#if RESET_N_PORT == 1
IO1CLR = BM(RESET_N);
#endif
}
static struct clk *_rcg_clk_get_parent(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
u32 cfg_regval;
struct clk_freq_tbl *freq;
u32 cmd_rcgr_regval;
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK)
return NULL;
if (has_mnd) {
m_regval = readl_relaxed(M_REG(rcg));
n_regval = readl_relaxed(N_REG(rcg));
d_regval = readl_relaxed(D_REG(rcg));
n_regval |= (n_regval >> 8) ? BM(31, 16) : BM(31, 8);
d_regval |= (d_regval >> 8) ? BM(31, 16) : BM(31, 8);
}
cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg));
cfg_regval &= CFG_RCGR_SRC_SEL_MASK | CFG_RCGR_DIV_MASK
| MND_MODE_MASK;
has_mnd = (has_mnd) &&
((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL);
cfg_regval &= ~MND_MODE_MASK;
for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
if (freq->div_src_val != cfg_regval)
continue;
if (has_mnd) {
if (freq->m_val != m_regval)
continue;
if (freq->n_val != n_regval)
continue;
if (freq->d_val != d_regval)
continue;
}
break;
}
if (freq->freq_hz == FREQ_END)
return NULL;
rcg->current_freq = freq;
return freq->src_clk;
}
// CC2420 voltage regulator enable pin
void SET_VREG_ACTIVE( void )
{
//PINSEL0 = 0x00000000;
//IO0DIR = IO0DIR | BM(VREG_EN);
#if VREG_EN_PORT == 0
IO0SET = BM(VREG_EN);
#endif
#if VREG_EN_PORT == 1
IO1SET = BM(VREG_EN);
#endif
}
// The CC2420 reset pin
void SET_RESET_INACTIVE( void )
{
//PINSEL0 = 0x00000000;
//IO0DIR = IO1DIR | BM(RESET_N);
#if RESET_N_PORT == 0
IO0SET = BM(RESET_N);
#endif
#if RESET_N_PORT == 1
IO1SET = BM(RESET_N);
#endif
}
void CC2420_SPI_DISABLE( void )
{
uint16 i = 0;
while(i < 1500) i++; //the delay is to construct enough holdup time of csn
//by huanghuan 2006.11.16
#if CSN_PORT == 0
IO0SET = BM(CSN);
#endif
#if CSN_PORT == 1
IO1SET = BM(CSN);
#endif
}
BOOL VALUE_OF_SFD( void )
{
BOOL result;
//PINSEL1 = 0x00000000;
//IO0DIR = IO0DIR & (~BM(SFD));
#if SFD_PORT == 0
if (IO0PIN & BM(SFD)) result = 1;
else result = 0;
#endif
#if SFD_PORT == 1
if (IO1PIN & BM(SFD)) result = 1;
else result = 0;
#endif
return(result);
}
void fillWall(struct TILE *map, int sy, int sx, int ft, int wt){
int y, x;
for(y = 1; y < sy - 1; y++){
for(x = 1; x < sx - 1; x++){
if(map[CM(y,sx,x)].tT == TILE_BLANK){
if(map[TL(y,sx,x)].tT == ft ||
map[TM(y,sx,x)].tT == ft ||
map[TR(y,sx,x)].tT == ft ||
map[CL(y,sx,x)].tT == ft ||
map[CR(y,sx,x)].tT == ft ||
map[BL(y,sx,x)].tT == ft ||
map[BM(y,sx,x)].tT == ft ||
map[BR(y,sx,x)].tT == ft){
map[CM(y,sx,x)].tT = wt;
}
}
}
}
for(y = 0; y < sy; y++){
for(x = 0; x < sx; x++){
if(y == 0){
if(map[S(y,sx,x)].tT == ft) map[C(y,sx,x)].tT = wt;
}
if(x == 0){
if(map[E(y,sx,x)].tT == ft) map[C(y,sx,x)].tT = wt;
}
if(y == sy - 1){
if(map[N(y,sx,x)].tT == ft) map[C(y,sx,x)].tT = wt;
}
if(x == sx - 1){
if(map[W(y,sx,x)].tT == ft) map[C(y,sx,x)].tT = wt;
}
}
}
}
void main(void)
{
unsigned char text[MAXSIZE];
unsigned char pat[MAXSIZE];
int answer, i;
printf("\nBoyer-Moore String Searching Program");
printf("\n====================================");
printf("\n\nText String --> ");
gets(text);
printf( "\nPattern String --> ");
gets(pat);
if ((answer = BM(text, pat)) >= 0) {
printf("\n ");
for (i = 1; i <= 6; i++)
printf(" %1d", i);
printf("\n");
for (i = 1; i <= 6; i++)
printf("0....5....");
printf("0");
printf("\n%s\n", text);
for (i = 0; i < answer; i++)
printf(" ");
printf("%s", pat);
printf("\n\nPattern Found at location %d", answer);
}
else
printf("\nPattern NOT FOUND.");
}
// This function used to initialize the onchip ADC for interrupt mode.
void initOnChipADC()
{
ADCSRA = BM(ADPS0) | BM(ADPS1) | BM(ADIE); // Enabling the interrupt as well.
ADMUX = BM(REFS0); // we are setting the channel to zero initially.
// enable the ADC now.
ADC_ENABLE();
// Delay.
nrk_spin_wait_us(ADC_SETUP_DELAY);
ADC_SET_CHANNEL(ACCEL_CHANEL_Z);
// start the ADC conversion;
ADCSRA |= BM(ADSC);
}
BOOL VALUE_OF_FIFOP( void )
{
BOOL result;
//PINSEL0 = 0x00000000;
//IO0DIR = IO0DIR & (~BM(FIFOP));
#if FIFOP_PORT == 0
if(IO0PIN & BM(FIFOP)) result = 1;
else result = 0;
#endif
#if FIFOP_PORT == 1
if(IO1PIN & BM(FIFOP)) result = 1;
else result = 0;
#endif
return(result);
}
void CC2420_SPI_ENABLE( void )
{
uint16 i = 0;
#if CSN_PORT == 0
IO0CLR = BM(CSN);
#endif
#if CSN_PORT == 1
IO1CLR = BM(CSN);
#endif
// @modified by huanghuan 2006.11.16
// the delay is to construct enough setup time of csn
// @TODO replace with hal_delay. you should not count on while for this delay
#pragma optimize=none
while(i < 500)
i++;
}
int main ()
{
uint16_t div;
nrk_int_disable();
// Configure relay port directions
DDRE |= 0x10;
socket_0_enable();
// Configure led port directions
DDRE |= 0x0c;
DDRD |= 0x00;
PORTD |= 0xff;
DDRF = 0;
socket_0_active=nrk_eeprom_read_byte(EEPROM_STATE_ADDR);
// turn outlet on if active or throttled for testing
if(socket_0_active==1 || socket_0_active==2)
{
socket_0_enable();
plug_led_green_set();
} else
{
socket_0_disable();
plug_led_green_clr();
}
// If PUD value set, then we expect it wasn't a clean reboot (unexpected restart).
// Try to force a proper watchdog reboot
if((MCUCR&0x10)!=0 )
{
//nrk_watchdog_enable();
nrk_int_disable();
MCUSR &= ~(1<<WDRF);
WDTCSR |= (1<<WDCE) | (1<<WDE);
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
// Disable interrupts to stop pending timers etc
while(1);
}
nrk_setup_uart (UART_BAUDRATE_115K2);
MCUCR |= BM(PUD);
nrk_init ();
nrk_time_set (0, 0);
tdma_set_error_callback(&tdma_error);
tdma_task_config();
nrk_create_taskset ();
nrk_start ();
return 0;
}
//-------------------------------------------------------------------------------------------------------
// void rfWaitForCrystalOscillator(void)
//
// DESCRIPTION:
// Waits for the crystal oscillator to become stable. The flag is polled via the SPI status byte.
//
// Note that this function will lock up if the SXOSCON command strobe has not been given before the
// function call. Also note that global interrupts will always be enabled when this function
// returns.
//-------------------------------------------------------------------------------------------------------
void halRfWaitForCrystalOscillator(void) {
uint8_t spiStatusByte;
// Poll the SPI status byte until the crystal oscillator is stable
do {
DISABLE_GLOBAL_INT();
spiStatusByte=cc2420GetStatus();
ENABLE_GLOBAL_INT();
} while (!(spiStatusByte & (BM(CC2420_XOSC16M_STABLE))));
} // halRfWaitForCrystalOscillator
uint8_t nrk_uart_data_ready_gps(uint8_t uart_num)
{
if(uart_num==0) {
if( UCSR0A & BM(RXC0) ) return 1;
}
if(uart_num==1) {
if(uart1_rx_buf_start != uart1_rx_buf_end) return 1;
//if(uart1_rx_signal > 0) return 1;
}
return 0;
}
static enum handoff branch_clk_handoff(struct clk *c)
{
struct branch_clk *branch = to_branch_clk(c);
u32 cbcr_regval;
cbcr_regval = readl_relaxed(CBCR_REG(branch));
if ((cbcr_regval & CBCR_BRANCH_OFF_BIT))
return HANDOFF_DISABLED_CLK;
if (branch->max_div) {
cbcr_regval &= BM(CBCR_CDIV_MSB, CBCR_CDIV_LSB);
cbcr_regval >>= CBCR_CDIV_LSB;
c->rate = cbcr_regval;
} else if (!branch->has_sibling) {
int main()
{
BM(1-1, (case1<O1, S1>()));
BM(1-2, (case2<O1, S1>()));
BM(2-1, (case1<O2, S2>()));
BM(2-2, (case2<O2, S2>()));
BM(3-1, (case1<O3, S3>()));
BM(3-2, (case2<O3, S3>()));
return 0;
}
/* Sample clock for 'ticks' reference clock ticks. */
static uint32_t run_measurement(unsigned ticks)
{
/* Stop counters and set the XO4 counter start value. */
writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
/* Wait for timer to become ready. */
while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
dmb();
/* Run measurement and wait for completion. */
writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
dmb();
/* Stop counters. */
writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
/* Return measured ticks. */
return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
}
int main ()
{
uint16_t div;
// Configure relay port directions
DDRE |= 0x10;
socket_0_enable();
// Configure led port directions
DDRE |= 0x0c;
DDRD |= 0x00;
PORTD |= 0xff;
DDRF = 0;
socket_0_active=nrk_eeprom_read_byte(EEPROM_STATE_ADDR);
if(socket_0_active==1)
{
socket_0_enable();
plug_led_green_set();
} else
{
socket_0_disable();
plug_led_green_clr();
}
MCUCR |= BM(PUD);
nrk_setup_uart (UART_BAUDRATE_115K2);
nrk_init ();
nrk_time_set (0, 0);
tdma_set_error_callback(&tdma_error);
tdma_task_config();
nrk_create_taskset ();
nrk_start ();
return 0;
}
[7] = acpu_freq_tbl_8226_1p4,
[1] = acpu_freq_tbl_8226_1p6,
};
static struct acpuclk_drv_data drv_data = {
.freq_tbl = acpu_freq_tbl_8226_1p1,
.pvs_tables = pvs_tables_8226,
.current_speed = &(struct clkctl_acpu_speed){ 0 },
.bus_scale = &bus_client_pdata,
.vdd_max_cpu = CPR_CORNER_12,
.src_clocks = {
[PLL0].name = "gpll0",
[ACPUPLL].name = "a7sspll",
},
.reg_data = {
.cfg_src_mask = BM(10, 8),
.cfg_src_shift = 8,
.cfg_div_mask = BM(4, 0),
.cfg_div_shift = 0,
.update_mask = RCG_CONFIG_UPDATE_BIT,
.poll_mask = RCG_CONFIG_UPDATE_BIT,
},
.power_collapse_khz = 96000,
.wait_for_irq_khz = 96000,
};
static int __init acpuclk_a7_probe(struct platform_device *pdev)
{
struct resource *res;
u32 i;
F_END
};
static struct rcg_clk usb_hs1_xcvr_clk = {
.b = {
.ctl_reg = (void *)USB_HS1_XCVR_FS_CLK_NS_REG,
.en_mask = BIT(9),
.reset_reg = (void *)USB_HS1_RESET_REG,
.reset_mask = BIT(0),
.halt_reg = (void *)CLK_HALT_DFAB_STATE_REG,
.halt_bit = 0,
},
.ns_reg = (void *)USB_HS1_XCVR_FS_CLK_NS_REG,
.md_reg = (void *)USB_HS1_XCVR_FS_CLK_MD_REG,
.root_en_mask = BIT(11),
.ns_mask = (BM(23, 16) | BM(6, 0)),
.set_rate = set_rate_mnd,
.freq_tbl = clk_tbl_usb,
.current_freq = &local_dummy_freq,
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &soc_clk_ops_8960,
},
};
#define CLK_SDC(i, n, h_r, h_c, h_b) \
struct rcg_clk i##_clk = { \
.b = { \
.ctl_reg = (void *)SDCn_APPS_CLK_NS_REG(n), \
.en_mask = BIT(9), \
.reset_reg = (void *)SDCn_RESET_REG(n), \
{ 1, 748800, ACPUPLL, 5, 0, LVL_HIGH, 1050000, 7 },
{ 1, 998400, ACPUPLL, 5, 0, LVL_HIGH, 1050000, 7 },
{ 0 }
};
static struct acpuclk_drv_data drv_data = {
.freq_tbl = acpu_freq_tbl,
.bus_scale = &bus_client_pdata,
.vdd_max_cpu = LVL_HIGH,
.vdd_max_mem = 1050000,
.src_clocks = {
[PLL0].name = "pll0",
[ACPUPLL].name = "pll14",
},
.reg_data = {
.cfg_src_mask = BM(2, 0),
.cfg_src_shift = 0,
.cfg_div_mask = BM(7, 3),
.cfg_div_shift = 3,
.update_mask = RCG_CONFIG_PGM_DATA_BIT | RCG_CONFIG_PGM_ENA_BIT,
.poll_mask = RCG_CONFIG_PGM_DATA_BIT,
},
.power_collapse_khz = 300000,
.wait_for_irq_khz = 300000,
};
static int __init acpuclk_9625_probe(struct platform_device *pdev)
{
struct resource *res;
u32 regval, i;
HALT, 3, 0), CLK(GRP_2D, BASIC, GRP_2D_NS_REG, GRP_2D_NS_REG, NULL, NULL, 0, CLK_HALT_STATEA_REG, HALT, 31, B(7), B(11), F_MASK_BASIC | (7 << 12), 0, set_rate_basic, clk_tbl_grp, NULL, AXI_GRP_2D, NULL, 0x5C00), CLK(GRP_3D_SRC, BASIC, GRP_NS_REG, GRP_NS_REG, NULL, NULL, 0, NULL, NOCHECK, 0, 0, B(11), F_MASK_BASIC | (7 << 12), 0, set_rate_basic, clk_tbl_grp, NULL, AXI_LI_GRP, chld_grp_3d_src, 0), CLK_SLAVE(GRP_3D, GRP_NS_REG, B(7), GRP_3D_SRC, CLK_HALT_STATEB_REG, HALT, 18, 0x5E00), CLK_SLAVE(IMEM, GRP_NS_REG, B(9), GRP_3D_SRC, CLK_HALT_STATEB_REG, HALT, 19, 0x5F00), CLK(LPA_CODEC, BASIC, LPA_NS_REG, LPA_NS_REG, NULL, NULL, 0, CLK_HALT_STATEC_REG, HALT, 6, B(9), 0, BM(1, 0), 0, set_rate_basic, clk_tbl_lpa_codec, NULL, NONE, NULL, 0x0F), CLK_MND8(CSI0, CSI_NS_REG, 24, 17, B(9), B(11), clk_tbl_csi, NULL, CLK_HALT_STATEB_REG, HALT, 9, 0x5F00), /* For global clocks to be on we must have GLBL_ROOT_ENA set */ CLK_1RATE(GLBL_ROOT, GLBL_CLK_ENA_SC_REG, 0, B(29), clk_tbl_axi, NULL, NOCHECK, 0, 0), /* Peripheral bus clocks. */ CLK_GLBL(ADM, GLBL_CLK_ENA_SC_REG, B(5), GLBL_CLK_STATE_REG, DELAY, 0, 0x4000), CLK_GLBL(CE, GLBL_CLK_ENA_SC_REG, B(6), GLBL_CLK_STATE_REG, HALT_VOTED, 6, 0x4D43),
static struct clk *_rcg_clk_get_parent(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
u32 cfg_regval;
struct clk_freq_tbl *freq;
u32 cmd_rcgr_regval;
/* Is there a pending configuration? */
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK)
return NULL;
/* Get values of m, n, d, div and src_sel registers. */
if (has_mnd) {
m_regval = readl_relaxed(M_REG(rcg));
n_regval = readl_relaxed(N_REG(rcg));
d_regval = readl_relaxed(D_REG(rcg));
/*
* The n and d values stored in the frequency tables are sign
* extended to 32 bits. The n and d values in the registers are
* sign extended to 8 or 16 bits. Sign extend the values read
* from the registers so that they can be compared to the
* values in the frequency tables.
*/
n_regval |= (n_regval >> 8) ? BM(31, 16) : BM(31, 8);
d_regval |= (d_regval >> 8) ? BM(31, 16) : BM(31, 8);
}
cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg));
cfg_regval &= CFG_RCGR_SRC_SEL_MASK | CFG_RCGR_DIV_MASK
| MND_MODE_MASK;
/* If mnd counter is present, check if it's in use. */
has_mnd = (has_mnd) &&
((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL);
/*
* Clear out the mn counter mode bits since we now want to compare only
* the source mux selection and pre-divider values in the registers.
*/
cfg_regval &= ~MND_MODE_MASK;
/* Figure out what rate the rcg is running at */
for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
if (freq->div_src_val != cfg_regval)
continue;
if (has_mnd) {
if (freq->m_val != m_regval)
continue;
if (freq->n_val != n_regval)
continue;
if (freq->d_val != d_regval)
continue;
}
break;
}
/* No known frequency found */
if (freq->freq_hz == FREQ_END)
return NULL;
rcg->current_freq = freq;
return freq->src_clk;
}
