コード例 #1
0
void SAMA5D3X_DramInit()
{
	BOARD_ConfigureDdram(DDRAM_MT47H128M16RT);
}
コード例 #2
0
//------------------------------------------------------------------------------
/// Bootstrap main application.
/// Transfer data from media to main memory and return the next application entry
/// point address.
//------------------------------------------------------------------------------
int main()
{
#if defined(BOOT_RECOVERY)
    unsigned char shallEraseBootstrap = 0; // Flag used to activate the boot recovery procedure
#endif

#if defined(at91cap9) && defined (FPGAINIT)
    unsigned int ret = 0;
#endif

    // Enable User Reset
    AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN | (0xA5<<24);

    //-------------------------------------------------------------------------
    // ROM Code Fixes
    //-------------------------------------------------------------------------
    // at91sam9261 with ROM code 1.4 fix : Disable USB pull-up
#ifdef at91sam9261
    AT91C_BASE_MATRIX->MATRIX_USBPCR = ~AT91C_MATRIX_USBPCR_PUON;
#endif


    //-------------------------------------------------------------------------
    // Test if at91bootstrap shall be erased (button pressed by user)
    //-------------------------------------------------------------------------
#if defined(BOOT_RECOVERY)
    shallEraseBootstrap = ShallEraseBootstrap();
#endif

    //-------------------------------------------------------------------------
    // Configure traces
    //-------------------------------------------------------------------------
    TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);

    TRACE_INFO_WP("\n\r");
    TRACE_INFO_WP("-- AT91bootstrap Project %s --\n\r", BOOTSTRAP_VERSION);
    TRACE_INFO_WP("-- %s\n\r", BOARD_NAME);
    TRACE_INFO_WP("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);

    TRACE_INFO("Setting: MCK = %dMHz\n\r", (int)(BOARD_MCK/1000000));

    //-------------------------------------------------------------------------
    // Enable I-Cache
    //-------------------------------------------------------------------------
    CP15_Enable_I_Cache();

    //-------------------------------------------------------------------------
    // Configure MPBLOCK
    //-------------------------------------------------------------------------
#if defined(at91cap9) && defined(FPGAINIT)
    ret = BOARD_FPGA_InitMPBlock();
    TRACE_INFO("return value BOARD_InitMPBlock() = 0x%x\n\r", ret);
#endif

    //-------------------------------------------------------------------------
    // Configure External memories supply
    //-------------------------------------------------------------------------

#if defined (at91cap9)

    // EBI 1V8
    //-------------------------------------------------------------------------
#if defined(VDDMEMSEL_EBI1V8)
    BOARD_ConfigureVddMemSel(VDDMEMSEL_1V8);
#endif
    // EBI 3V3
    //-------------------------------------------------------------------------
#if defined(VDDMEMSEL_EBI3V3)
    BOARD_ConfigureVddMemSel(VDDMEMSEL_3V3);
#endif

#if !defined(VDDMEMSEL_EBI1V8) && !defined(VDDMEMSEL_EBI3V3)
#error No external memories power supply selected
#endif // VDDMEMSEL

#endif // at91cap9

    //-------------------------------------------------------------------------
    // Configure external RAM where the application will be transfered
    //-------------------------------------------------------------------------

    // SDRAM
    //-------------------------------------------------------------------------
#if defined(DESTINATION_sdram)
    TRACE_INFO("Init SDRAM\n\r");
    BOARD_ConfigureSdram(BOARD_SDRAM_BUSWIDTH);
#endif

    // DDRAM
    //-------------------------------------------------------------------------
#if defined(DESTINATION_ddram)
    TRACE_INFO("Init DDRAM\n\r");
    BOARD_ConfigureDdram(0, BOARD_DDRAM_BUSWIDTH);
#endif

    // BCRAM
    //-------------------------------------------------------------------------
#if defined(DESTINATION_bcram)
    TRACE_INFO("Init BCRAM\n\r");
    BOARD_ConfigureBcram(BOARD_BCRAM_BUSWIDTH);
#endif

    // Check that a destination memory has be selected
#if !defined(DESTINATION_sdram) && \
        !defined(DESTINATION_ddram) && \
        !defined(DESTINATION_bcram)
#error No destination memory selected
#endif

    //-------------------------------------------------------------------------
    // Configure access to memory and transfer data from memory to external RAM
    //-------------------------------------------------------------------------

    // DataFlash
    //-------------------------------------------------------------------------
#if defined(ORIGIN_dataflash)
#if defined(BOOT_RECOVERY)
    if (shallEraseBootstrap)
        BOOT_AT45_EraseBoot();
    else
#endif //BOOT_RECOVERY
        BOOT_AT45_CopyBin(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // SerialFlash
    //-------------------------------------------------------------------------
#if defined(ORIGIN_serialflash)
    BOOT_AT26_CopyBin(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // NandFlash
    //-------------------------------------------------------------------------
#if defined(ORIGIN_nandflash)
#if defined(BOOT_RECOVERY)
    if (shallEraseBootstrap)
        BOOT_NAND_EraseBoot();
    else
#endif //BOOT_RECOVERY
        BOOT_NAND_CopyBin(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // SDcard
    //-------------------------------------------------------------------------
#if defined(ORIGIN_sdcard)
    BOOT_SDcard_CopyFile(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // NorFlash
    //-------------------------------------------------------------------------
#if defined(ORIGIN_norflash)
    BOOT_NOR_CopyBin(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // Eeprom
    //-------------------------------------------------------------------------
#if defined(ORIGIN_eeprom)
    BOOT_EEPROM_CopyBin(tabDesc, TDESC_LISTSIZE(tabDesc));
#endif

    // Check that an origin memory has be selected
#if !defined(ORIGIN_dataflash) && \
        !defined(ORIGIN_serialflash) && \
        !defined(ORIGIN_nandflash) && \
        !defined(ORIGIN_sdcard) && \
        !defined(ORIGIN_norflash) && \
        !defined(ORIGIN_eeprom)
#error No origin memory selected
#endif

    //-------------------------------------------------------------------------
    // Jump to external RAM
    //-------------------------------------------------------------------------
#ifdef DEBUG_DUMP_MEMORY
    UTIL_DbguDumpMemory(tabDesc[0].dest, 0x200);
#endif

    TRACE_INFO("Jump to 0x%08x\n\r", tabDesc[0].dest);
    GoToJumpAddress(tabDesc[0].dest, MACH_TYPE);

    return 0;//never reach
}
コード例 #3
0
ファイル: main.c プロジェクト: Reedgarden/WRS-SW
//------------------------------------------------------------------------------
/// Applet code for initializing the external RAM.
//------------------------------------------------------------------------------
int main(int argc, char **argv)
{
	struct _Mailbox *pMailbox = (struct _Mailbox *) argv;
	unsigned int ramType = 0;
	unsigned int bufferSize, bufferAddr, memoryOffset;
	unsigned int bytesToWrite;
	unsigned int tempBufferAddr;
	unsigned int dataBusWidth = 0;
	unsigned int ddrModel = 0;

	LowLevelInit();

	TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);



	/*    *AT91C_PMC_PCER = AT91C_ID_PIOA;
	 *AT91C_PIOA_PDR = (1<<31);
	 *AT91C_PIOA_OER = (1<<31);
	 *AT91C_PIOA_BSR = (1<<31);
	 *AT91C_PIOA_PER = (1<<0);
	 *AT91C_PIOA_OER = (1<<0);

	 *AT91C_PMC_PCKR = (1<<8); // select master clock
	 *AT91C_PMC_SCER = (1<<8); // ENABLE PCK0*/

	TRACE_INFO("Statup: PMC_MCKR %x MCK = %d command = %d\n\r", *AT91C_PMC_MCKR, BOARD_MCK, pMailbox->command);
	// ----------------------------------------------------------
	// INIT:
	// ----------------------------------------------------------
	if (pMailbox->command == APPLET_CMD_INIT) {

		// Initialize PMC
		//	BOARD_RemapRam();


		// Enable User Reset
		AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN | (0xA5<<24);


		ramType = pMailbox->argument.inputInit.ramType;
		dataBusWidth = pMailbox->argument.inputInit.dataBusWidth;
		ddrModel = pMailbox->argument.inputInit.ddrModel;

		//#if (DYN_TRACES == 1)
		//        traceLevel = pMailbox->argument.inputInit.traceLevel;
		//#endif

		TRACE_INFO("-- EXTRAM ISP Applet %s --\n\r", SAM_BA_APPLETS_VERSION);
		TRACE_INFO("-- %s\n\r", BOARD_NAME);
		TRACE_INFO("-- Compiled: %s %s %s --\n\r", __DATE__, __TIME__, __GIT__);
		TRACE_INFO("INIT command:\n\r");

		TRACE_INFO("\tCommunication link type : %d\n\r", pMailbox->argument.inputInit.comType);
		TRACE_INFO("\tData bus width : %d bits\n\r", dataBusWidth);
		if (ramType == TYPE_SDRAM) {
			TRACE_INFO("\tExternal RAM type : %s\n\r", "SDRAM");
		}
		else {
			if (ramType == TYPE_DDRAM) {
				TRACE_INFO("\tExternal RAM type : %s\n\r", "DDRAM");
			}
			else {
				TRACE_INFO("\tExternal RAM type : %s\n\r", "PSRAM");
			}
		}

#if defined(at91cap9) || defined(at91sam9m10) || defined(at91sam9g45)
		TRACE_INFO("\tInit EBI Vdd : %s\n\r", (pMailbox->argument.inputInit.VddMemSel)?"3.3V":"1.8V");
		BOARD_ConfigureVddMemSel(pMailbox->argument.inputInit.VddMemSel);
#endif //defined(at91cap9)

		if (pMailbox->argument.inputInit.ramType == TYPE_SDRAM) {
			// Configure SDRAM controller
			TRACE_INFO("\tInit SDRAM...\n\r");
#if defined(PINS_SDRAM)
			BOARD_ConfigureSdram(dataBusWidth);
#endif
		}
		else if (pMailbox->argument.inputInit.ramType == TYPE_PSRAM) {
			TRACE_INFO("\tInit PSRAM...\n\r");
#if defined(at91sam3u4)            
			BOARD_ConfigurePsram();
#endif            
		}
		else {
			// Configure DDRAM controller
#if defined(at91cap9dk) || defined(at91sam9m10) || defined(at91sam9g45)
			TRACE_INFO("\tInit DDRAM ... (model : %d)\n\r", ddrModel);
			BOARD_ConfigureVddMemSel(VDDMEMSEL_1V8);
			BOARD_ConfigureDdram(0, dataBusWidth);
			//	    ddramc_hw_init();
#endif
		}
		TRACE_INFO("\tInit successful.\n\r");
	}

	// ----------------------------------------------------------
	// LIST_BAD_BLOCK: (Check DDR)
	// ----------------------------------------------------------
	else if (pMailbox->command == APPLET_CMD_LIST_BAD_BLOCKS)
	{

		// Test external RAM access
		if (ExtRAM_TestOk()) {
			pMailbox->status = APPLET_SUCCESS;
		}
		else {
			pMailbox->status = APPLET_FAIL;
		}

		pMailbox->argument.outputInit.bufferAddress = ((unsigned int) &end);
		pMailbox->argument.outputInit.bufferSize = 0;
		pMailbox->argument.outputInit.memorySize = EXTRAM_SIZE;
	}


	// ----------------------------------------------------------
	// WRITE:
	// ----------------------------------------------------------
	else if (pMailbox->command == APPLET_CMD_WRITE)
	{
		memoryOffset = pMailbox->argument.inputWrite.memoryOffset;
		bufferAddr = pMailbox->argument.inputWrite.bufferAddr;
		bytesToWrite = pMailbox->argument.inputWrite.bufferSize;
		tempBufferAddr = bufferAddr+memoryOffset;

		TRACE_INFO("WRITE arguments : offset 0x%x, run 0x%x, of 0x%x Bytes\n\r",
				memoryOffset, tempBufferAddr, bytesToWrite);

		pMailbox->argument.outputWrite.bytesWritten = 0;

		/*
		 * We must define the following
		 * 	-  MACH_TYPE_xxx
		 * 	- Setup the kernel tagged list (http://www.arm.linux.org.uk/developer/booting.php#4)
		 * 		 first 16KiB of RAM.
		 *
		 * 		we recommend to load at 32KiB into RAM
		 */

		//Fake the end of the applet because we will not be able to do anything after this step
		if (bytesToWrite < EXTRAM_SIZE)
		{
				pMailbox->status = APPLET_SUCCESS;
		}
		else
		{
			pMailbox->status = APPLET_FAIL;
		}
		pMailbox->command = ~(pMailbox->command);

		//Going to
		((VFptr *)(EXTRAM_ADDR+memoryOffset))();

	}

exit :
	// Acknowledge the end of command
	TRACE_INFO("\tEnd of applet (command : %x --- status : %x)\n\r", pMailbox->command, pMailbox->status);

	// Notify the host application of the end of the command processing
	pMailbox->command = ~(pMailbox->command);

	return 0;
}
コード例 #4
0
ファイル: board_lowlevel.c プロジェクト: chenzhengxi/2060-83
/**
 * \brief Performs the low-level initialization of the chip.
 * This includes EFC and master clock configuration.
 * It also enable a low level on the pin NRST triggers a user reset.
 */
extern WEAK void LowLevelInit( void )
{
    uint8_t i;
    uint32_t _dwTimeout = 0;
    volatile uint32_t read = 0;
    
    if ((uint32_t)LowLevelInit < EBI_CS0_ADDR) /* Code not in external mem */
    {
        /* Switch to PLL + prescaler */
        read = PMC->PMC_MCKR;
        read &= ~(PMC_MCKR_CSS_Msk);
        read |= PMC_MCKR_CSS_MAIN_CLK;
        PMC->PMC_MCKR = read;
        while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
        
        PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(64) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
        _dwTimeout = 0;
        while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (_dwTimeout++ < CLOCK_TIMEOUT));
        
        PMC->CKGR_PLLAR = 0;

        /* Initialize PLLA */
        PMC->CKGR_PLLAR = CKGR_PLLAR_STUCKTO1
                        | CKGR_PLLAR_MULA(199) 
                        | CKGR_PLLAR_OUTA(0)
                        | CKGR_PLLAR_PLLACOUNT(63)
                        | CKGR_PLLAR_DIVA(3);
        _dwTimeout = 0;
        while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (_dwTimeout++ < CLOCK_TIMEOUT));
        
        /* Wait for the master clock if it was already initialized */
        for ( _dwTimeout =  0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; );

        /* Switch to fast clock
        **********************/
        /* Switch to main oscillator + prescaler */
        read = PMC->PMC_MCKR;
        read &= ~(PMC_MCKR_MDIV_Msk);
        read |= (PMC_MCKR_MDIV_PCK_DIV3 | PMC_MCKR_PLLADIV2_DIV2);
        PMC->PMC_MCKR = read;
       
        /* Wait for the master clock if it was already initialized */
        for ( _dwTimeout =  0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; );
      
        /* Switch to main oscillator + prescaler */
        read = PMC->PMC_MCKR;
        read &= ~(PMC_MCKR_PRES_Msk);
        read |= PMC_MCKR_PRES_CLOCK;
        PMC->PMC_MCKR = read;

        /* Wait for the master clock if it was already initialized */
        for ( _dwTimeout =  0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; );

        /* Switch to PLL + prescaler */
        read = PMC->PMC_MCKR;
        read &= ~(PMC_MCKR_CSS_Msk);
        read |= PMC_MCKR_CSS_PLLA_CLK;
        PMC->PMC_MCKR = read;

        /* Wait for the master clock if it was already initialized */
        for ( _dwTimeout =  0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; );
    } 

    /* Initialize AIC */
    AIC->AIC_IDCR = 0xFFFFFFFF;
    AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler;

    for (i = 1; i < 31; i++) {
        AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler;
    }
    AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;

    /* Unstack nested interrupts */
    for (i = 0; i < 8 ; i++) {

        AIC->AIC_EOICR = 0;
    }

    /* Remap */
    BOARD_RemapRam();
    BOARD_ConfigureDdram();
}
コード例 #5
0
ファイル: main.c プロジェクト: insofter/factory
//------------------------------------------------------------------------------
/// Applet code for initializing the external RAM.
//------------------------------------------------------------------------------
int main(int argc, char **argv)
{
    struct _Mailbox *pMailbox = (struct _Mailbox *) argv;
    unsigned int ramType = 0;
    unsigned int dataBusWidth = 0;
    unsigned int ddrModel = 0;
    unsigned int baseAddress = 0;
    unsigned int *ramAddr = (unsigned int *) EXTRAM_ADDR;
    unsigned int comType = 0;

    TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);

    // ----------------------------------------------------------
    // INIT:
    // ----------------------------------------------------------
    if (pMailbox->command == APPLET_CMD_INIT) {
        // Save info of communication link
        comType = pMailbox->argument.inputInit.comType;

#if (TRACE_LEVEL==0) && (DYN_TRACES==0) 
        if (comType == DBGU_COM_TYPE){
            // Function TRACE_CONFIGURE_ISP wiil be bypass due to the 0 TRACE_LEVEL. We shall reconfigure the baut rate.
            DBGU_Configure(DBGU_STANDARD, 115200, BOARD_MCK); 
        }
#endif        
        // Enable User Reset
        AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN | (0xA5<<24);

        ramType = pMailbox->argument.inputInit.ramType;
        dataBusWidth = pMailbox->argument.inputInit.dataBusWidth;
        ddrModel = pMailbox->argument.inputInit.ddrModel;
        baseAddress = pMailbox->argument.inputInit.baseAddress;

#if (DYN_TRACES == 1)
        traceLevel = pMailbox->argument.inputInit.traceLevel;
#endif

        TRACE_INFO("-- EXTRAM Applet %s --\n\r", SAM_BA_APPLETS_VERSION);
        TRACE_INFO("-- %s\n\r", BOARD_NAME);
        TRACE_INFO("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
        TRACE_INFO("INIT command:\n\r");

        TRACE_INFO("\tCommunication link type : %d\n\r", pMailbox->argument.inputInit.comType);
        TRACE_INFO("\tData bus width : %d bits\n\r", dataBusWidth);
        if (ramType == TYPE_SDRAM) {
           TRACE_INFO("\tExternal RAM type : %s\n\r", "SDRAM");
        }
        else {
            if (ramType == TYPE_DDRAM) {
                TRACE_INFO("\tExternal RAM type : %s\n\r", "DDRAM");
            }
            else {
                TRACE_INFO("\tExternal RAM type : %s\n\r", "PSRAM");
            }
        }

#if defined(at91cap7) || defined(at91cap9) || defined(at91sam9m10) || defined(at91sam9g45)
        TRACE_INFO("\tInit EBI Vdd : %s\n\r", (pMailbox->argument.inputInit.VddMemSel)?"3.3V":"1.8V");
        BOARD_ConfigureVddMemSel(pMailbox->argument.inputInit.VddMemSel);
#endif //defined(at91cap9)

        if (pMailbox->argument.inputInit.ramType == TYPE_SDRAM) {
            // Configure SDRAM controller
            TRACE_INFO("\tInit SDRAM...\n\r");
#if defined(PINS_SDRAM)
            BOARD_ConfigureSdram(dataBusWidth);
#endif
        }
        else if (pMailbox->argument.inputInit.ramType == TYPE_PSRAM) {
            TRACE_INFO("\tInit PSRAM...\n\r");
#if defined(at91sam3u)
            BOARD_ConfigurePsram();
#endif
        }
        else {
            // Configure DDRAM controller
#if defined(at91sam9m10) || defined(at91sam9g45)
            TRACE_INFO("\tInit DDRAM ... (model : %d)\n\r", ddrModel);
            BOARD_ConfigureDdram(baseAddress, ddrModel, dataBusWidth);
            
            if (baseAddress != (unsigned int)AT91C_BASE_DDR2C) {
                ramAddr = (unsigned int *)EXTRAM_ADDR_2;
            }
#elif defined(at91cap9dk)
            TRACE_INFO("\tInit DDRAM ... (model : %d)\n\r", ddrModel);
            BOARD_ConfigureDdram(ddrModel, dataBusWidth);
#endif
        }

        // Test external RAM access
        if (ExtRAM_TestOk(ramAddr)) {

            pMailbox->status = APPLET_SUCCESS;
        }
        else {
            pMailbox->status = APPLET_FAIL;
        }

        pMailbox->argument.outputInit.bufferAddress = ((unsigned int) &end);
        pMailbox->argument.outputInit.bufferSize = 0;
        pMailbox->argument.outputInit.memorySize = EXTRAM_SIZE;

        TRACE_INFO("\tInit successful.\n\r");
    }

    // Acknowledge the end of command
    TRACE_INFO("\tEnd of applet (command : %x --- status : %x)\n\r", pMailbox->command, pMailbox->status);

    // Notify the host application of the end of the command processing
    pMailbox->command = ~(pMailbox->command);
    // Send ACK character
    if (comType == DBGU_COM_TYPE) {
        DBGU_PutChar(0x6);
    }
    return 0;
}