cache_size, cache_base);
flash->erase(flash, to_flash_offset(flash, cache_base), cache_size);
/* we will start at the beginning again */
cache = cache_base;
}
// 4. write mrc data with flash->write()
printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n",
cache);
flash->write(flash, to_flash_offset(flash, cache),
current->mrc_data_size + sizeof(*current), current);
}
BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
update_mrc_cache, NULL),
};
#endif
struct mrc_data_container *find_current_mrc_cache(void)
{
struct mrc_data_container *cache_base;
u32 cache_size;
cache_size = get_mrc_cache_region(&cache_base);
if (cache_base == NULL) {
printk(BIOS_ERR, "%s: could not find MRC cache area\n",
__func__);
return NULL;
}
*/
static void set_pci_irqs(void *unused)
{
/* Write PCI_INTR regs 0xC00/0xC01 */
write_pci_int_table();
/* Write IRQs for all devicetree enabled devices */
write_pci_cfg_irqs();
}
/*
* Hook this function into the PCI state machine
* on entry into BS_DEV_ENABLE.
*/
BOOT_STATE_INIT_ENTRIES(pci_irq_update) = {
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY,
set_pci_irqs, NULL),
};
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb800_enable(device_t dev)
{
struct southbridge_amd_cimx_sb800_config *sb_chip =
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
printk(BIOS_DEBUG, "sb800_enable() ");
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
/* the first sb800 device */
#if !defined(__PRE_RAM__)
/* selected cbmem can be initialized early in ramstage. Additionally, that
* means cbmem console can be reinitialized early as well. The post_device
* function is empty since cbmem was initialized early in ramstage. */
static void init_cbmem_pre_device(void *unused)
{
cbmem_initialize();
#if CONFIG_CONSOLE_CBMEM
cbmemc_reinit();
#endif /* CONFIG_CONSOLE_CBMEM */
}
BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = {
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY,
init_cbmem_pre_device, NULL),
};
void cbmem_add_lb_mem(struct lb_memory *mem)
{
unsigned long base;
unsigned long top;
base = (unsigned long)cbmem_base();
top = (unsigned long)get_top_aligned();
lb_add_memory_range(mem, LB_MEM_TABLE, base, top - base);
}
void cbmem_list(void)
{
unsigned int i;
//0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd
E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1
E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en
E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en
E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en
E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en
E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en
E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en
E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis
E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis
E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis
E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis
E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis
E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis
E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis
E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis
REG_SCRIPT_END,
};
static void perf_power(void *unused)
{
printk(BIOS_DEBUG, "Applying perf/power settings.\n");
reg_script_run(perf_power_settings);
}
BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = {
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL),
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL),
};
*
* EAX = APM_CNT_GNVS_UPDATE
* EBX = gnvs pointer
* EDX = APM_CNT
*/
asm volatile (
"outb %%al, %%dx\n\t"
: /* ignore result */
: "a" (APM_CNT_GNVS_UPDATE),
"b" ((u32)gnvs),
"d" (APM_CNT)
);
}
/*
* Finalize system before payload boot if not in ChromeOS environment.
*/
#if !CONFIG_CHROMEOS
static void finalize_boot(void *unused)
{
outb(0xcb, 0xb2);
}
BOOT_STATE_INIT_ENTRIES(finalize) = {
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY,
finalize_boot, NULL),
};
#endif
