/**
* Complete a full configuration of the UART.
**/
static BT_ERROR canSetConfig(BT_HANDLE hCan, BT_CAN_CONFIG *pConfig) {
volatile LPC17xx_CAN_REGS *pRegs = hCan->pRegs;
BT_ERROR Error = BT_ERR_NONE;
canSetBaudrate(hCan, pConfig->ulBaudrate);
switch(pConfig->eMode) {
case BT_UART_MODE_POLLED: {
if(hCan->eMode != BT_CAN_MODE_POLLED) {
if(hCan->hTxFifo) {
BT_CloseHandle(hCan->hTxFifo);
hCan->hTxFifo = NULL;
}
if(hCan->hRxFifo) {
BT_CloseHandle(hCan->hRxFifo);
hCan->hRxFifo = NULL;
}
// Disable TX and RX interrupts
pRegs->CANIER &= ~LPC17xx_CAN_IER_RIE; // Disable the interrupt
hCan->eMode = BT_CAN_MODE_POLLED;
}
break;
}
case BT_UART_MODE_BUFFERED:
{
if(hCan->eMode != BT_CAN_MODE_BUFFERED) {
if(!hCan->hRxFifo && !hCan->hTxFifo) {
hCan->hRxFifo = BT_FifoCreate(pConfig->usRxBufferSize, sizeof(BT_CAN_MESSAGE), 0, &Error);
hCan->hTxFifo = BT_FifoCreate(pConfig->usTxBufferSize, sizeof(BT_CAN_MESSAGE), 0, &Error);
pRegs->CANIER |= LPC17xx_CAN_IER_RIE; // Enable the interrupt
hCan->eMode = BT_CAN_MODE_BUFFERED;
}
}
break;
}
}
LPC17xx_CAN_COMMON_REGS *pCMN = CAN_COMMON;
pCMN->LPC17xx_CAN_AFMR |= LPC17xx_CAN_AFMR_ACCBP;
return Error;
}
/**
* Complete a full configuration of the UART.
**/
static BT_ERROR uartSetConfig(BT_HANDLE hUart, BT_UART_CONFIG *pConfig) {
volatile LM3Sxx_UART_REGS *pRegs = hUart->pRegs;
BT_ERROR Error = BT_ERR_NONE;
uartSetBaudrate(hUart, pConfig->ulBaudrate);
uartDisable(hUart);
// Set parity, data length, and number of stop bits.
pRegs->LCRH = (pConfig->ucDataBits - 5) << 5;
pRegs->LCRH |= (pConfig->ucStopBits) << 3;
if (pConfig->ucParity == BT_UART_PARITY_ODD) pRegs->LCRH |= LM3Sxx_UART_LCRH_ODD;
if (pConfig->ucParity == BT_UART_PARITY_EVEN) pRegs->LCRH |= LM3Sxx_UART_LCRH_EVEN;
if (pConfig->ucParity == BT_UART_PARITY_MARK) pRegs->LCRH |= LM3Sxx_UART_LCRH_MARK;
if (pConfig->ucParity == BT_UART_PARITY_SPACE) pRegs->LCRH |= LM3Sxx_UART_LCRH_SPACE;
// Clear the flags register.
pRegs->FR = 0;
uartEnable(hUart);
switch(pConfig->eMode) {
case BT_UART_MODE_POLLED: {
if(hUart->eMode != BT_UART_MODE_POLLED) {
if(hUart->hTxFifo) {
BT_CloseHandle(hUart->hTxFifo);
hUart->hTxFifo = NULL;
}
if(hUart->hRxFifo) {
BT_CloseHandle(hUart->hRxFifo);
hUart->hRxFifo = NULL;
}
// Disable TX and RX interrupts
pRegs->IM &= ~(LM3Sxx_UART_INT_RX | LM3Sxx_UART_INT_RT); // Disable the interrupt
hUart->eMode = BT_UART_MODE_POLLED;
}
break;
}
case BT_UART_MODE_BUFFERED:
{
if(hUart->eMode != BT_UART_MODE_BUFFERED) {
if(!hUart->hRxFifo && !hUart->hTxFifo) {
hUart->hRxFifo = BT_FifoCreate(pConfig->ulRxBufferSize, 1, 0, &Error);
hUart->hTxFifo = BT_FifoCreate(pConfig->ulTxBufferSize, 1, 0, &Error);
pRegs->IM |= LM3Sxx_UART_INT_RX | LM3Sxx_UART_INT_RT; // Enable the interrupt
hUart->eMode = BT_UART_MODE_BUFFERED;
}
}
break;
}
default:
// Unsupported operating mode!
break;
}
return BT_ERR_NONE;
}
/**
* Complete a full configuration of the SPI.
**/
static BT_ERROR spiSetConfig(BT_HANDLE hSpi, BT_SPI_CONFIG *pConfig) {
volatile LPC17xx_SPI_REGS *pRegs = hSpi->pRegs;
BT_ERROR Error = BT_ERR_NONE;
const BT_RESOURCE *pResource = BT_GetIntegratedResource(hSpi->pDevice, BT_RESOURCE_ENUM, 0);
if (pResource->ulStart == 0) {
pRegs->CR &= ~(LPC17xx_SPI_CR_DSS_MASK << 8);
pRegs->CR |= (pConfig->ucDataBits & LPC17xx_SPI_CR_DSS_MASK) << 8;
pRegs->CR &= ~(LPC17xx_SPI_CR_CPOL | LPC17xx_SPI_CR_CPHA);
if (pConfig->eCPOL)
pRegs->CR |= LPC17xx_SPI_CR_CPOL;
if (pConfig->eCPHA)
pRegs->CR |= LPC17xx_SPI_CR_CPHA;
}
else {
pRegs->CR0 = (pConfig->ucDataBits - 1) & LPC17xx_SPI_CR0_DSS_MASK;
pRegs->CR0 |= pConfig->eCPOL << 6;
pRegs->CR0 |= pConfig->eCPHA << 7;
}
spiSetBaudrate(hSpi, pConfig->ulBaudrate);
switch(pConfig->eMode) {
case BT_SPI_MODE_POLLED: {
if(hSpi->eMode != BT_SPI_MODE_POLLED) {
if(hSpi->hTxFifo) {
BT_CloseHandle(hSpi->hTxFifo);
hSpi->hTxFifo = NULL;
}
if(hSpi->hRxFifo) {
BT_CloseHandle(hSpi->hRxFifo);
hSpi->hRxFifo = NULL;
}
// Disable TX and RX interrupts
//@@pRegs->IER &= ~LPC17xx_SPI_IER_RBRIE; // Disable the interrupt
hSpi->eMode = BT_SPI_MODE_POLLED;
}
break;
}
case BT_SPI_MODE_BUFFERED:
{
if(hSpi->eMode != BT_SPI_MODE_BUFFERED) {
if(!hSpi->hRxFifo && !hSpi->hTxFifo) {
hSpi->hRxFifo = BT_FifoCreate(pConfig->ulRxBufferSize, 1, 0, &Error);
hSpi->hTxFifo = BT_FifoCreate(pConfig->ulTxBufferSize, 1, 0, &Error);
//@@pRegs->IER |= LPC17xx_SPI_IER_RBRIE; // Enable the interrupt
hSpi->eMode = BT_SPI_MODE_BUFFERED;
}
}
break;
}
default:
// Unsupported operating mode!
break;
}
return BT_ERR_NONE;
}
