/**************************************************************************//**
* @brief vPortSetupTimerInterrupt
* Override the default definition of vPortSetupTimerInterrupt() that is weakly
* defined in the FreeRTOS Cortex-M3, which set source of system tick interrupt
*****************************************************************************/
void vPortSetupTimerInterrupt(void)
{
/* Set our timer's data used as system ticks*/
ulTimerReloadValueForOneTick = SYSTICK_LOAD_VALUE;
#if (configUSE_TICKLESS_IDLE == 1)
xMaximumPossibleSuppressedTicks = TIMER_CAPACITY / (SYSTICK_LOAD_VALUE);
ulStoppedTimerCompensation = TIMER_COMPENSATION / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ);
#endif /* (configUSE_TICKLESS_IDLE == 1) */
/* Ensure LE modules are accessible */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable access to BURTC registers */
RMU_ResetControl(rmuResetBU, false);
/* Configure BURTC as system tick source */
BURTC_Init_TypeDef burtcInit = BURTC_INIT_DEFAULT;
burtcInit.mode = burtcModeEM3; /* BURTC is enabled to EM3 */
burtcInit.clkSel = burtcClkSelULFRCO; /* Select ULFRCO as clock source */
burtcInit.clkDiv = burtcClkDiv_1; /* Choose 2kHz ULFRCO clock frequency */
/* Initialization of BURTC */
BURTC_Init(&burtcInit);
/* Disable interrupt generation from BURTC */
BURTC_IntDisable(BURTC_IF_COMP0);
/* Tick interrupt MUST execute at the lowest interrupt priority. */
NVIC_SetPriority(BURTC_IRQn, 255);
/* Enable interrupts */
NVIC_ClearPendingIRQ(BURTC_IRQn);
NVIC_EnableIRQ(BURTC_IRQn);
BURTC_CompareSet(0, SYSTICK_LOAD_VALUE);
BURTC_IntClear(BURTC_IF_COMP0);
BURTC_IntEnable(BURTC_IF_COMP0);
BURTC_CounterReset();
}
/***************************************************************************//**
* @brief Initialize BURTC
*
* @details
* Configures the BURTC peripheral.
*
* @note
* Before initialization, BURTC module must first be enabled by clearing the
* reset bit in the RMU, i.e.
* @verbatim
* RMU_ResetControl(rmuResetBU, rmuResetModeClear);
* @endverbatim
* Compare channel 0 must be configured outside this function, before
* initialization if enable is set to true. The counter will always be reset.
*
* @param[in] burtcInit
* Pointer to BURTC initialization structure
******************************************************************************/
void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
{
uint32_t ctrl;
uint32_t presc;
/* Check initializer structure integrity */
EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0);
/* Clock divider must be between 1 and 128, really on the form 2^n */
EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128));
/* Ignored compare bits during low power operation must be less than 7 */
/* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7 */
EFM_ASSERT(burtcInit->lowPowerComp <= 6);
/* You cannot enable the BURTC if mode is set to disabled */
EFM_ASSERT((burtcInit->enable == false) ||
((burtcInit->enable == true)
&& (burtcInit->mode != burtcModeDisable)));
/* Low power mode is only available with LFRCO or LFXO as clock source */
EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)
|| ((burtcInit->clkSel == burtcClkSelULFRCO)
&& (burtcInit->lowPowerMode == burtcLPDisable)));
/* Calculate prescaler value from clock divider input */
/* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
value 1 will select a 2kHz ULFRCO clock, while any other value will
select a 1kHz ULFRCO clock source. */
presc = divToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
if (burtcInit->enable)
{
BURTC_FreezeEnable(true);
}
/* Modification of LPMODE register requires sync with potential ongoing
* register updates in LF domain. */
regSync(BURTC_SYNCBUSY_LPMODE);
/* Configure low power mode */
BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode);
/* New configuration */
ctrl = (BURTC_CTRL_RSTEN
| (burtcInit->mode)
| (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT)
| (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT)
| (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT)
| (presc << _BURTC_CTRL_PRESC_SHIFT)
| (burtcInit->clkSel)
| (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));
/* Clear interrupts */
BURTC_IntClear(0xFFFFFFFF);
/* Set new configuration */
BURTC->CTRL = ctrl;
/* Enable BURTC and counter */
if (burtcInit->enable)
{
/* To enable BURTC counter, we need to disable reset */
BURTC_Enable(true);
/* Clear freeze */
BURTC_FreezeEnable(false);
}
}
/**************************************************************************//**
* @brief BURTC Interrupt Handler clears the flag
*****************************************************************************/
void BURTC_IRQHandler(void)
{
/* Clear interrupt source */
BURTC_IntClear(BURTC_IFC_COMP0);
}
