/*
* ======== Boot_configurePll2834x ========
*/
Void Boot_configurePll2834x(UInt16 pllcrDIV, UInt16 pllstsDIVSEL)
{
/* check if running in Limp mode; if yes, abort */
if (REG(PLLSTS_REG) & PLLSTS_MCLKSTS_BIT) {
Boot_limpAbort();
}
EALLOW;
/* set max divide select (DIVSEL = 0) */
REG(PLLSTS_REG) &= ~PLLSTS_DIVSEL_BITS;
/* temporarily disable failed oscillator detect */
REG(PLLSTS_REG) |= PLLSTS_MCLKOFF_BIT;
/* set the new PLL multiplier value */
REG(PLLCR_REG) = pllcrDIV;
/* wait for the PLL to relock */
while (!(REG(PLLSTS_REG) & PLLSTS_PLLLOCKS_BIT)) {
};
/* re-enable failed oscillator detection */
REG(PLLSTS_REG) &= ~PLLSTS_MCLKOFF_BIT;
/* set divide select bits (DIVSEL) */
REG(PLLSTS_REG) |= pllstsDIVSEL << PLLSTS_DIVSEL_SHIFTBITS;
EDIS;
}
/*
* ======== Boot_configurePllDivs ========
*
*/
Void Boot_configurePllDivs(UInt SPLLIMULT, UInt SPLLFMULT, UInt SYSDIVSEL,
UInt M3SSDIVSEL)
{
#if 0
UInt missDetect;
#endif
UInt sysdiv;
UInt m3div;
UInt allow;
/* check if running in Limp mode; if yes, call abort function */
if (REG(MCLKSTS_REG) & MCLKFLG_M) {
Boot_limpAbort();
}
/* enable M3 access to protected registers */
allow = REG(SYSCTL_MWRALLOW);
REG(SYSCTL_MWRALLOW) = SYSCTL_UNLOCK;
#if 0
/* test teams see instabilities w/disabling MCLK, leave enabled for now */
/* get missing clock detect enable status */
missDetect = REG(MCLKEN_REG);
/* temporarily disable the MCLK detection logic */
REG(MCLKEN_REG) &= ~MCLKDETEN_M;
#endif
/* set SYS and M3 dividers to maximum */
REG(SYSDIVSEL_REG) = (REG(SYSDIVSEL_REG) & ~SYSDIVSEL_M) | SYSDIVSEL_DIV8;
REG(M3SSDIVSEL_REG) = (REG(M3SSDIVSEL_REG) & ~M3SSDIVSEL_M)
| M3SSDIVSEL_DIV4;
sysdiv = SYSDIVSEL_DIV8;
m3div = M3SSDIVSEL_DIV4;
/* disable and bypass the PLL */
REG(SYSPLLCTL_REG) &= ~(SPLLCLKEN_M | SPLLEN_M);
/* set integer multiplier */
REG(SYSPLLMULT_REG) = (REG(SYSPLLMULT_REG) & ~SPLLIMULT_M) | SPLLIMULT;
/* set fractional multipler */
REG(SYSPLLMULT_REG) = (REG(SYSPLLMULT_REG) & ~SPLLFMULT_M) | SPLLFMULT;
/* enable PLL to start lock */
REG(SYSPLLCTL_REG) |= SPLLEN_M;
/* wait for PLL lock */
while ((REG(SYSPLLSTS_REG) & SYSPLLLOCKS_M == 0)) {
};
/* enable PLL to clock CPUs */
REG(SYSPLLCTL_REG) |= SPLLCLKEN_M;
/* step M3SS divider downwards from max to target value */
while(m3div != M3SSDIVSEL) {
if (m3div == M3SSDIVSEL_DIV4 ) { /* if DIV4, step to DIV2 */
REG(M3SSDIVSEL_REG) = (REG(M3SSDIVSEL_REG) & ~M3SSDIVSEL_M)
| M3SSDIVSEL_DIV2;
m3div = M3SSDIVSEL_DIV2;
Boot_stepDelay(15);
}
else { /* for DIV2, step to DIV1 */
REG(M3SSDIVSEL_REG) = (REG(M3SSDIVSEL_REG) & ~M3SSDIVSEL_M)
| M3SSDIVSEL_DIV1;
m3div = M3SSDIVSEL_DIV1;
Boot_stepDelay(15);
}
}
/* step SYSDIV divider downwards from max to target value */
while(sysdiv != SYSDIVSEL) {
if (sysdiv == SYSDIVSEL_DIV8 ) { /* if DIV8, step to DIV4 */
REG(SYSDIVSEL_REG) = (REG(SYSDIVSEL_REG) & ~SYSDIVSEL_M)
| SYSDIVSEL_DIV4;
sysdiv = SYSDIVSEL_DIV4;
Boot_stepDelay(15);
}
else if (sysdiv == SYSDIVSEL_DIV4 ) { /* if DIV4, step to DIV2 */
REG(SYSDIVSEL_REG) = (REG(SYSDIVSEL_REG) & ~SYSDIVSEL_M)
| SYSDIVSEL_DIV2;
sysdiv = SYSDIVSEL_DIV2;
Boot_stepDelay(15);
}
else { /* for DIV2, step to DIV1 */
REG(SYSDIVSEL_REG) = (REG(SYSDIVSEL_REG) & ~SYSDIVSEL_M)
| SYSDIVSEL_DIV1;
sysdiv = SYSDIVSEL_DIV1;
Boot_stepDelay(15);
}
}
#if 0
/* restore missing clock detect enable state on entry */
REG(MCLKEN_REG) |= (missDetect & MCLKDETEN_M);
#endif
/* restore M3 access protect setting */
REG(SYSCTL_MWRALLOW) = allow;
}
