/**
* Function Compile_Ratsnest
* Create the entire board ratsnest.
* Must be called after a board change (changes for
* pads, footprints or a read netlist ).
* @param aDC = the current device context (can be NULL)
* @param aDisplayStatus : if true, display the computation results
*/
void PCB_BASE_FRAME::Compile_Ratsnest( wxDC* aDC, bool aDisplayStatus )
{
wxString msg;
GetBoard()->m_Status_Pcb = 0; // we want a full ratsnest computation, from the scratch
ClearMsgPanel();
// Rebuild the full pads and net info list
RecalculateAllTracksNetcode();
if( aDisplayStatus )
{
msg.Printf( wxT( " %d" ), m_Pcb->GetPadCount() );
AppendMsgPanel( wxT( "Pads" ), msg, RED );
msg.Printf( wxT( " %d" ), m_Pcb->GetNetCount() );
AppendMsgPanel( wxT( "Nets" ), msg, CYAN );
}
/* Compute the full ratsnest
* which can be see like all the possible links or logical connections.
* some of them are active (no track connected) and others are inactive
* (when tracks connect pads)
* This full ratsnest is not modified by track editing.
* It changes only when a netlist is read, or footprints are modified
*/
Build_Board_Ratsnest();
// Compute the pad connections due to the existing tracks (physical connections)
TestConnections();
/* Compute the active ratsnest, i.e. the unconnected links
*/
TestForActiveLinksInRatsnest( 0 );
// Redraw the active ratsnest ( if enabled )
if( GetBoard()->IsElementVisible(RATSNEST_VISIBLE) && aDC )
DrawGeneralRatsnest( aDC, 0 );
if( aDisplayStatus )
SetMsgPanel( m_Pcb );
}
void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC * DC, bool display_status_pcb )
/******************************************************************************/
/*
Génère le chevelu complet de la carte.
Doit etre appelé APRES le calcul de connectivité
Doit etre appelé apres changement de structure de la carte (modif
de pads, de nets, de modules).
Si display_status_pcb : affichage des résultats en bas d'ecran
*/
{
wxString msg;
affiche_chevelu = TRUE;
/* construction de la liste des coordonnées des pastilles */
m_Pcb->m_Status_Pcb = 0; /* réinit total du calcul */
build_liste_pads() ;
MsgPanel->EraseMsgBox() ; /* effacement du bas d'ecran */
msg.Printf( wxT(" %d"),m_Pcb->m_NbPads) ;
Affiche_1_Parametre(this, 1, wxT("pads"), msg,RED) ;
msg.Printf( wxT(" %d"),m_Pcb->m_NbNets) ;
Affiche_1_Parametre(this, 8, wxT("Nets"), msg,CYAN) ;
reattribution_reference_piste(display_status_pcb);
Build_Board_Ratsnest(DC ); /* calcul du chevelu general */
test_connexions(DC); /* determine les blocks de pads connectés par
les pistes existantes */
Tst_Ratsnest(DC, 0 ); /* calcul du chevelu actif */
// Reaffichage des chevelus actifs
if( g_Show_Ratsnest ) DrawGeneralRatsnest( DC, 0 );
if ( display_status_pcb ) Affiche_Infos_Status_Pcb(this);
}
/* function TestForActiveLinksInRatsnest
* determine the active links inside the full ratsnest
*
* I used an algorithm inspired by the "Lee algorithm".
* The idea is all pads must be connected by a physical track or a logical track
* a physical track is the existing track on copper layers.
* a logical track is the link that must be activated (visible) if
* no track found between 2 pads.
* The algorithm explore the existing full ratnest
* This is a 2 steps algorithm (executed for each net).
* - First:
* Initialise for each pad the subratsnest id to its subnet value
* explore the full ratnest (relative to the net) and active a link each time at least one pad of
* the given link is not connected to an other pad by a track ( subratsnest = 0)
* If the 2 pads linked have both the subratsnest id = 0, a new subratsnest value is created
* - Second:
* explore the full ratnest (relative to the net) and find a link that links
* 2 pads having different subratsnest values
* Active the link and merge the 2 subratsnest value.
*
* This is usually fast because the ratsnest is not built here: it is just explored
* to see what link must be activated
*/
void PCB_BASE_FRAME::TestForActiveLinksInRatsnest( int aNetCode )
{
RATSNEST_ITEM* rats;
D_PAD* pad;
NETINFO_ITEM* net;
if( m_Pcb->GetPadCount() == 0 )
return;
if( (m_Pcb->m_Status_Pcb & LISTE_RATSNEST_ITEM_OK) == 0 )
Build_Board_Ratsnest();
for( int net_code = 1; net_code < (int) m_Pcb->GetNetCount(); net_code++ )
{
net = m_Pcb->FindNet( net_code );
wxCHECK_RET( net != NULL,
wxString::Format( wxT( "Net code %d not found!" ), net_code ) );
if( aNetCode && (net_code != aNetCode) )
continue;
// Create subratsnests id from subnets created by existing tracks:
int subratsnest = 0;
for( unsigned ip = 0; ip < net->m_PadInNetList.size(); ip++ )
{
pad = net->m_PadInNetList[ip];
int subnet = pad->GetSubNet();
pad->SetSubRatsnest( subnet );
subratsnest = std::max( subratsnest, subnet );
}
for( unsigned ii = net->m_RatsnestStartIdx; ii < net->m_RatsnestEndIdx; ii++ )
{
m_Pcb->m_FullRatsnest[ii].m_Status &= ~CH_ACTIF;
}
// First pass - activate links for not connected pads
rats = &m_Pcb->m_FullRatsnest[0];
tst_links_between_pads( subratsnest,
rats + net->m_RatsnestStartIdx,
rats + net->m_RatsnestEndIdx );
// Second pass activate links between blocks (Iteration)
while( subratsnest > 1 )
{
subratsnest = tst_links_between_blocks( net, m_Pcb->m_FullRatsnest );
}
}
m_Pcb->SetUnconnectedNetCount( 0 );
unsigned cnt = 0;
for( unsigned ii = 0; ii < m_Pcb->GetRatsnestsCount(); ii++ )
{
if( m_Pcb->m_FullRatsnest[ii].IsActive() )
cnt++;
}
m_Pcb->SetUnconnectedNetCount( cnt );
}
