/**
* ============================================================================
* @n@b Osal_cppiBeginMemAccess
*
* @b brief
* @n The function is used to indicate that a block of memory is
* about to be accessed. If the memory block is cached then this
* indicates that the application would need to ensure that the
* cache is updated with the data from the actual memory.
*
* @param[in] ptr
* Address of memory block
*
* @param[in] size
* Size of memory block
* @retval
* Not Applicable
* =============================================================================
*/
void Osal_cppiBeginMemAccess (void *ptr, uint32_t size)
{
/* Recommended sequence for cache operations is:
* 1) Disable all interrupts
* 2) Perform the cache block operation
* 3) Wait until the cache operation is done either by polling
* the corresponding WC register or using _mfence ()
* instruction.
* 4) Enable interrupts back.
*/
/* Disable all interrupts */
Osal_biosInterruptCsEnter ();
/* Invalidate L1D cache and wait until operation is complete.
* Use this approach if L2 cache is not enabled
*/
CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
/* Invalidate L2 cache. This should invalidate L1D as well.
* Wait until operation is complete.
*/
/* CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT); */
/* Invalidate the prefetch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();
/* Enable back interrupts */
Osal_biosInterruptCsExit ();
return;
}
/**
* @b Description
* @n
* The function is used by the SRIO driver to indicate that
* its about to access a block of memory and we need to ensure
* that the cache contents for this block are invalidated before
* we try and use it.
*
* @param[in] ptr
* Pointer to the buffer which is being accessed
* @param[in] size
* Size of the buffer which is to be accessed.
*
* @retval
* None
*/
void Osal_srioBeginMemAccess(void* ptr, uint32_t size)
{
#if 0
CACHE_invL1d (ptr, size, CACHE_WAIT);
/* Cleanup the prefectch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Cleanup the prefetch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();
/* Invalidate the cache. */
CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
/**
* @b Description
* @n
* The function is used to indicate that a block of memory is
* about to be accessed. If the memory block is cached then this
* indicates that the application would need to ensure that the
* cache is updated with the data from the actual memory.
*
* @param[in] ptr
* Address of memory block
* @param[in] size
* Size of memory block
*
* @retval
* Not Applicable
*/
void Osal_qmssBeginMemAccess (void *ptr, uint32_t size)
{
#if 0
/* Invalidate L1D cache and wait until operation is complete.
* Use this approach if L2 cache is not enabled */
CACHE_invL1d (ptr, size, CACHE_WAIT);
/* Cleanup the prefectch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Cleanup the prefetch buffer also. */
CSL_XMC_invalidatePrefetchBuffer();
/* Invalidate the cache. */
CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
extern void __interrupt _c_int00()
{
/*-------------------------------------------------------------------------
* After a reset, the device should have invalidated caches. The caches will
* still be configured as they were prior to the reset. Since this code was
* loaded into L2, we will ensure that L2 is configured as all sram.
*------------------------------------------------------------------------*/
CACHE_setL2Size (CACHE_0KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_setL1PSize(CACHE_L1_32KCACHE);
/*-------------------------------------------------------------------------
* Set up the stack pointer in b15.
* The stack pointer points 1 word past the top of the stack, so subtract
* 1 word from the size. also the sp must be aligned on an 8-byte boundary
*------------------------------------------------------------------------*/
__asm("\t MVKL\t\t __TI_STACK_END - 4, SP");
__asm("\t MVKH\t\t __TI_STACK_END - 4, SP");
__asm("\t AND\t\t ~7,SP,SP");
/*-------------------------------------------------------------------------
* Set up the global data page pointer in b14.
*------------------------------------------------------------------------*/
__asm("\t MVKL\t\t __TI_STATIC_BASE,DP");
__asm("\t MVKH\t\t __TI_STATIC_BASE,DP");
/*-------------------------------------------------------------------------
* disable cache for all addrs over 0x1000:0000
*------------------------------------------------------------------------*/
memset((void*)0x01848040, 0, 960);
/*-------------------------------------------------------------------------
* disable mpax registers 3 and above
*------------------------------------------------------------------------*/
memset((void*)0x08000018, 0, 104);
/*-------------------------------------------------------------------------
* disable msmc ses mpax registers except for the first one at each pri lev
*------------------------------------------------------------------------*/
if (DNUM == 0)
{
int i;
for (i=0; i < 16; i++)
memset((void*)(0x0bc00600 + (i * 0x40) + 8), 0, 0x38);
}
/*-------------------------------------------------------------------------
* Set up floating point registers
*------------------------------------------------------------------------*/
FADCR = 0; FMCR = 0;
/*-------------------------------------------------------------------------
* Setup platform specifics, i.e. uarts, ethernet, etc.
*------------------------------------------------------------------------*/
if (DNUM == 0)
{
/*---------------------------------------------------------------------
* Check if Boot time init configuration is loaded
*
* This code is reading l2 memory written by the host. The values were
* written before this code began running, so the cache invalidate at
* reset should ensure that when we read these values we will miss l1 and
* read directly from l2.
*--------------------------------------------------------------------*/
platform_init_config config;
config.pllm = 0; // Original configuraion : default 0 -> 1 GHz
if (init_config.magic_number == 0xBABEFACE)
config.pllm = init_config.dsp_pll_multiplier;
/* Platform initialization */
platform_init_flags flags;
flags.pll = 0x1;
flags.ddr = 0x1;
flags.tcsl = 0x1;
flags.phy = 0x0;
flags.ecc = 0x1;
platform_init(&flags, &config);
platform_uart_init();
platform_uart_set_baudrate(DEF_INIT_CONFIG_UART_BAUDRATE);
memset((void*)&flags, 0 , sizeof(platform_init_flags));
memset((void*)&config, 0, sizeof(platform_init_config));
flags.pll = 0;
flags.ddr = 0;
flags.tcsl = 1;
flags.phy = 1;
flags.ecc = 0;
platform_init(&flags, &config);
Init_MAC(0);
Init_MAC(1);
Init_Switch(1506);
}
/*-------------------------------------------------------------------------
* Once we write 0 to the boot magic addr, the host can proceed with the
* loading of another program that will subsequently run. We should ensure
* that the caches are written back and clean at this point so that a
* subsequent writeback opertation will not clobber the program loaded
* from the host. It is also clearly important that the loaded program
* did not write over the L2 area containing the remainder of this code.
*------------------------------------------------------------------------*/
BOOT_MAGIC_CONTENTS = 0;
CACHE_wbInvL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);
wait_for_interrupt();
/*-------------------------------------------------------------------------
* We will now wait until an external entity writes the address to which we
* should jump
*------------------------------------------------------------------------*/
while (1)
{
/*---------------------------------------------------------------------
* invalidate the address so that we pick up the actual memory written by
* the external entity.
*--------------------------------------------------------------------*/
CACHE_invL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);
void (*entry)() = (void (*)())(BOOT_MAGIC_CONTENTS);
/*---------------------------------------------------------------------
* If we have a non null pointer then we will branch to it. This
* essentially marks the end of this routine and the start of another,
* so we should ensure that the caches are written back and clean at
* this point so that the following program starts with a clean cache
* system.
*
* It is also clearly important that the loaded program did not write
* over the L2 area containing this reset code. Since this reset code
* is entirely resident in the last 1/4 of L2, this area should not
* contain initialized data or code in the following program.
*--------------------------------------------------------------------*/
if (entry)
{
flushCache();
(*entry)();
}
}
}