int can_Config(
struct inode *inode,
int target,
unsigned long val1,
unsigned long val2
)
{
unsigned int minor = MINOR(inode->i_rdev);
switch(target) {
case CONF_ACC:
DBGprint(DBG_DATA,("mask = 0x%lx, code = 0x%lx", val1, val2));
AccMask[minor] = val1;
AccCode[minor] = val2;
CAN_SetMask(minor, AccCode[minor], AccMask[minor]);
break;
case CONF_ACCM:
DBGprint(DBG_DATA,("acc_mask=0x%lx", val1));
AccMask[minor] = val1;
CAN_SetMask(minor, AccCode[minor], AccMask[minor]);
break;
case CONF_ACCC:
DBGprint(DBG_DATA,("acc_code=0x%lx", val1));
AccCode[minor] = val1;
CAN_SetMask(minor, AccCode[minor], AccMask[minor]);
break;
case CONF_TIMING:
Baud[minor] = val1;
CAN_SetTiming(minor,(int) val1);
break;
case CONF_OMODE:
CAN_SetOMode( minor, (int) val1);
break;
#if CAN_USE_FILTER
case CONF_FILTER:
Can_FilterOnOff( minor, (int) val1 );
break;
case CONF_FENABLE:
Can_FilterMessage( minor, (int) val1, 1);
break;
case CONF_FDISABLE:
Can_FilterMessage( minor, (int) val1, 0);
break;
#endif
default:
DBGout();
return(-EINVAL);
}
return 0;
}
int can_Config(
struct inode *inode,
struct file *file,
int target,
unsigned long val1,
unsigned long val2
)
{
unsigned int minor = iminor(inode);
int rx_fifo = ((struct _instance_data *)(file->private_data))->rx_index;
int ret;
DBGin();
ret = -EINVAL;
switch(target) {
case CONF_ACC: /* set the first code/mask pair */
#if defined(IMX35) || defined(IMX25)
ret = CAN_SetMask(minor, 0, val2, val1);
#else
ret = CAN_SetMask(minor, val2, val1);
#endif
break;
case CONF_ACCM: /* set the first mask only */
#if defined(IMX35) || defined(IMX25)
ret = CAN_SetMask(minor, 0, AccCode[minor][0], val1);
#else
ret = CAN_SetMask(minor, AccCode[minor], val1);
#endif
break;
case CONF_ACCC: /* the first code only */
#if defined(IMX35) || defined(IMX25)
ret = CAN_SetMask(minor, 0, val1, AccMask[minor][0]);
#else
ret = CAN_SetMask(minor, val1, AccMask[minor]);
#endif
break;
#if defined(IMX35) || defined(IMX25)
case CONF_ACC1: /* set the first additional code/mask pair */
ret = CAN_SetMask(minor, 1, val2, val1);
break;
case CONF_ACC2:
ret = CAN_SetMask(minor, 2, val2, val1);
break;
case CONF_ACC3:
ret = CAN_SetMask(minor, 3, val2, val1);
break;
case CONF_ACC4:
ret = CAN_SetMask(minor, 4, val2, val1);
break;
case CONF_ACC5:
ret = CAN_SetMask(minor, 5, val2, val1);
break;
case CONF_ACC6:
ret = CAN_SetMask(minor, 6, val2, val1);
break;
case CONF_ACC7:
ret = CAN_SetMask(minor, 7, val2, val1);
break;
#endif
case CONF_TIMING:
ret = CAN_SetTiming(minor,(int) val1);
if (0 == ret) {
Baud[minor] = val1;
} else {
ret = -EINVAL;
}
break;
case CONF_OMODE:
ret = CAN_SetOMode( minor, (int) val1);
break;
#if CAN_USE_FILTER
case CONF_FILTER:
Can_FilterOnOff( minor, (int) val1 );
break;
case CONF_FENABLE:
Can_FilterMessage( minor, (int) val1, 1);
break;
case CONF_FDISABLE:
Can_FilterMessage( minor, (int) val1, 0);
break;
#endif
case CONF_LISTEN_ONLY_MODE:
ret = CAN_SetListenOnlyMode( minor, (int) val1);
break;
case CONF_SELF_RECEPTION:
DBGprint(DBG_DATA,
("setting selfreception of minor %d to %d\n", minor, (int)val1));
selfreception[minor][rx_fifo] = (int)val1;
ret = 0;
break;
case CONF_TIMESTAMP:
use_timestamp[minor] = (int)val1;
ret = 0;
break;
case CONF_WAKEUP:
wakeup[minor] = (int)val1;
ret = 0;
break;
case CONF_BTR:
ret = CAN_SetBTR(minor, (int)val1, (int)val2);
break;
default:
ret = -EINVAL;
}
DBGout();
return ret;
}
/*
* CAN_ChipReset - performs the first initialization or re-iniatalization of the chip
*
* set INIT mode
* initialize the I/O pin modes as CAN TX/RX
* initialize the CAN bit timing
* initialize message buffers
* initialize interrut sources
*/
int CAN_ChipReset (int board)
{
int i;
DBGin("CAN_ChipReset");
/* printk("CAN_ChipReset\n"); */
/*
* Initialize Port AS PAR to have Can TX/RX signals enabled
*/
#define MCF5282_GPIO_PASPAR (*(volatile u16 *)(void *)(0x40100056))
MCF5282_GPIO_PASPAR = 0x0FF0;
/* printk("I/O %p %04x\n",
(volatile u16 *)(void *)(0x40100056), MCF5282_GPIO_PASPAR); */
/*
* go to INIT mode
* Any configuration change/initialization requires that the FlexCAN be
* frozen by either asserting the HALT bit in the
* module configuration register or by reset.
* For Init_CAN() we choose reset.
*/
CANresetw(board, canmcr, CAN_MCR_FRZ);
/* CANoutw(board, canmcr, 0x0080); */
CANsetw(board, canmcr, CAN_MCR_SOFT_RST);
udelay(10);
/* Test Reset Status */
if(CANtestw(board, canmcr, CAN_MCR_SOFT_RST) != 0) {
MOD_DEC_USE_COUNT;
DBGout();return -1;
}
udelay(10);
/* Initialize the transmit and receive pin modes in control register 0 */
CANout(board, canctrl0,
CAN_CTRL0_DISABLE_BOFF_INT /* disable Bus-Off Interrupt */
+ CAN_CTRL0_DISABLE_ERR_INT /* disable Error Interrupt */
+ 0 /* 4 , logic RX level */
+ 0 /* 1 , logic TX level */
);
/* CANresetw(board, canmcr, CAN_MCR_HALT); */
CAN_SetTiming(board, Baud[board]);
/*
* Select the internal arbitration mode
* LBUF in CANCTRL1
* LBUF Lowest Buffer Transmitted First
* The LBUF bit defines the transmit-first scheme.
* 0 = Message buffer with lowest ID is transmitted first.
* 1 = Lowest numbered buffer ist transmitted first.
*
* should have no impact here, the driver is using only one
* TX object
*
* !! change the order of the next two statements !!
*/
CANset(board, canctrl1, CAN_CTRL1_LBUF);
CANreset(board, canctrl1, CAN_CTRL1_LBUF);
/*
* Initialize message buffers.
* The control/status word of all message buffers are written
* as an inactive receive message buffer.
*/
for(i = 0; i < 16; i++) {
CAN_WRITE_CTRL(i, REC_CODE_NOT_ACTIVE, 0);
}
/* create a transmit object, that can be used for all kinds of messages */
/* some receive objects
* - RECEIVE_STD_OBJ to receive all standard frames
* - RECEIVE_EXT_OBJ to receive all extended frames
* - ??
*/
CAN_WRITE_CTRL(RECEIVE_STD_OBJ, REC_CODE_NOT_ACTIVE, 0);
CAN_WRITE_OID(RECEIVE_STD_OBJ, 0); /* set IDE - extended bit to zero */
CAN_SetMask (board, AccCode[board], AccMask[board] );
CAN_WRITE_CTRL(RECEIVE_STD_OBJ, REC_CODE_EMPTY, 8);
/* The IDE-Bit (Bit 4) must be set to 1 for extended */
CAN_WRITE_CTRL(RECEIVE_EXT_OBJ, REC_CODE_NOT_ACTIVE, 0);
CAN_WRITE_XOID(RECEIVE_EXT_OBJ, 0); /* set IDE - extended bit to 1 */
CAN_SetMask (board, AccCode[board], AccMask[board] );
CAN_WRITE_CTRL(RECEIVE_EXT_OBJ, REC_CODE_EMPTY, 8);
#if 0
/* RTR Receive Object !!! No such thing possible !!! */
CAN_WRITE_CTRL(RECEIVE_RTR_OBJ, REC_CODE_NOT_ACTIVE, 0);
CAN_WRITE_OID(RECEIVE_RTR_OBJ, 1);
CAN_SetMask (board, AccCode[board], AccMask[board] );
CAN_WRITE_CTRL(RECEIVE_RTR_OBJ, REC_CODE_EMPTY, 8);
#endif
/* CAN_register_dump(); */
/* CAN_object_dump(RECEIVE_STD_OBJ); */
/* CAN_object_dump(RECEIVE_EXT_OBJ); */
/* CAN_object_dump(RECEIVE_RTR_OBJ); */
/*
* - Initialize IARB[3:0] to a non zero value in CANMCR
* ( This is done in CAN-ChipReset() )
* - Set the required mask bits in the IMASK register (for all message
* buffer interrupts) in CANCTRL0 for bus off and error interrupts,
* and in CANMCR for WAKE interrupt.
*/
/* dont't forget error int's ! */
CANsetw(board, canmcr, 1);
CANoutw(board, imask,
(1 << RECEIVE_STD_OBJ)
+(1 << RECEIVE_EXT_OBJ)
+(1 << TRANSMIT_OBJ));
/* printk("imask at %p \n", &((canregs_t *)can_base[board])->imask ); */
/* CAN_register_dump(); */
DBGout();
return 0;
}
