void udp_echo_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct
ip_addr *addr, u16_t port)
{
uint8_t buffer[512];
if (p != NULL)
{
if(pbuf_copy_partial(p, buffer, p->tot_len,0) != p->tot_len)
{
LWIP_DEBUGF(LWIP_DBG_ON, ("pbuf_copy_partial failed\r\n"));
}
else
{
buffer[p->tot_len] = '\0';
LWIP_DEBUGF(LWIP_DBG_ON, ("UDP got data:%s\r\n", buffer));
CAN_WriteData(HW_CAN1, 2, CAN_TX_ID, buffer, 8);
}
// send received packet back to sender
udp_sendto(pcb, p, addr, port);
// free the pbuf
pbuf_free(p);
}
}
int main(void)
{
DelayInit();
GPIO_QuickInit(HW_GPIOE, 6, kGPIO_Mode_OPP);
UART_QuickInit(UART0_RX_PD06_TX_PD07, 115200);
printf("CAN test\r\n");
CAN_QuickInit(CAN1_TX_PE24_RX_PE25, 125*1000);
/* FIFO deep is 0+6 = 6
Once FIFO is enabled, MB0-5 cannot used as normal MB, MB0-5 used as RxFIFO and they automaically configed as Rx MB
*/
CAN_SetRxFIFO(HW_CAN1);
CAN_CallbackInstall(HW_CAN1, CAN_ISR);
CAN_ITDMAConfig(HW_CAN1, CAN_RX_FIFO_MB, kCAN_IT_RX);
while(1)
{
CAN_WriteData(HW_CAN1, CAN_TX_MB, CAN_TX_ID, (uint8_t *)"CAN TEST", 8); /* 使用邮箱2 发送ID:0x10 发送 "CAN TEST" */
DelayMs(500);
GPIO_ToggleBit(HW_GPIOE, 6);
}
}
/***************************************************************************//**
* @brief
* Send the data from the Message Object message.
*
* @details
* If message is configured as tx and remoteTransfer = 0, calling this function
* will send the data of this Message Object if its parameters are correct.
* If message is tx and remoteTransfer = 1, this function will set the data of
* message to the RAM and exit, the data will be automatically sent after
* reception of a remote frame.
* If message is rx and remoteTransfer = 1, this function will send a remote
* frame to the corresponding id.
* If message is rx and remoteTransfer = 0, the user shouldn't call this
* function. It will also send a remote frame.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
* @param[in] message
* Message Object
*
* @param[in] wait
* If true, wait for the end of the transfer between the MIRx registers and
* the RAM to exit. If false, exit immediately, the transfer can still be
* in progress.
******************************************************************************/
void CAN_SendMessage(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message,
bool wait)
{
CAN_MIR_TypeDef * mir = &can->MIR[interface];
/* Make sure msgNum is in the correct range */
EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
/* Make sure dlc is in the correct range */
EFM_ASSERT(message->dlc <= _CAN_MIR_CTRL_DLC_MASK);
CAN_ReadyWait(can, interface);
/* Set LEC to unused value to be sure it is reset to 0 after sending */
BUS_RegMaskedWrite(&can->STATUS, _CAN_STATUS_LEC_MASK, 0x7);
/* Set which registers to read from the RAM */
mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
| CAN_MIR_CMDMASK_ARBACC
| CAN_MIR_CMDMASK_CONTROL;
/* Send reading request and wait (3 to 6 cpu cycle) */
CAN_SendRequest(can, interface, message->msgNum, true);
/* Reset MSGVAL */
mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
CAN_SendRequest(can, interface, message->msgNum, true);
/* Set which registers to write to the RAM */
mir->CMDMASK |= CAN_MIR_CMDMASK_DATAA
| CAN_MIR_CMDMASK_DATAB;
/* If tx = 1 and remoteTransfer = 1, nothing is sent */
if ( ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0)
|| ((mir->ARB & _CAN_MIR_ARB_DIR_MASK) == _CAN_MIR_ARB_DIR_RX)) {
mir->CTRL |= CAN_MIR_CTRL_TXRQST;
/* DATAVALID is set only if it is not sending a remote message */
if ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0) {
mir->CTRL |= CAN_MIR_CTRL_DATAVALID;
}
}
/* Set the Data length Code */
mir->CTRL = (mir->CTRL & ~_CAN_MIR_CTRL_DLC_MASK)
| message->dlc;
/* Configure the id */
if (message->extended) {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
| (message->id << _CAN_MIR_ARB_ID_SHIFT)
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| CAN_MIR_ARB_XTD_EXT;
} else {
EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | _CAN_MIR_ARB_XTD_MASK))
| (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
| (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
| CAN_MIR_ARB_XTD_STD;
}
/* Set the data */
CAN_WriteData(can, interface, message);
/* Send writing request */
CAN_SendRequest(can, interface, message->msgNum, wait);
}
