static void ZipDec_Restart(void)
{
CHIP_REG_AND(ZIPDEC_CTRL , ~ZIPDEC_EN);
ZipDec_Disable();
udelay(100);
ZipDec_Enable();
ZipDec_Reset();
CHIP_REG_OR(ZIPDEC_CTRL , ZIPDEC_EN);
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_QueueEn();
}
if(zipdec_param.wait_mode==ZIPDEC_WAIT_INT)
{
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_IntEn(ZIPDEC_QUEUE_DONE_INT);
}
else
{
ZipDec_IntEn(ZIPDEC_DONE_INT);
}
ZipDec_IntEn(ZIPDEC_TIMEOUT_INT);
}
}
PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
{
// Reset the analog die register
ANA_REG_AND (ANA_HWRST_STATUS, ~0xFFF);
ANA_REG_OR (ANA_HWRST_STATUS, (val&0xFFF));
// Reset the HW_RST
CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
}
PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
{
if(TYPE_RESET == type)
{
// Switch IRAM from DCAM to ARM
REG32 (AHB_CTL1) |= BIT_0;
CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
}
else
{
//wrong type, TODO
}
}
static void pd_shutdown_config(struct shutdown_cfg *cfg,
struct pd_reg_bit *pd_reg)
{
/*enable all xtl for simply config. xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
unsigned int i = 0, j;
unsigned int reg_value = 0;
if ((!cfg) || (cfg[0].pd_shutdown_id == RESERVED_NUM) || (pd_reg == NULL)) {
return;
}
/*collecting the current system mode, like TD only ..etc.*/
while (cfg[i].pd_shutdown_id != RESERVED_NUM) {
j = 0;
while (pd_reg[j].pd_shutdown_id != RESERVED_NUM) {
if (cfg[i].pd_shutdown_id == pd_reg[j].pd_shutdown_id) {
break;
}
++j;
}
if (pd_reg[j].pd_shutdown_id == RESERVED_NUM) {
continue;
}
if (pd_reg[j].pd_reg != -1) {
if(cfg[i].iso_on_delay != NO_USED) {
reg_value = cfg[i].iso_on_delay << __ffs(pd_reg[j].iso_on_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].iso_on_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
}
if(cfg[i].pwr_on_seq_delay != NO_USED) {//pwr_on_seq_delay
reg_value = cfg[i].pwr_on_seq_delay
<< __ffs(pd_reg[j].pwr_on_seq_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_seq_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
}
if(cfg[i].pwr_on_delay != NO_USED) {//pwr_on_delay
reg_value = cfg[i].pwr_on_delay << __ffs(pd_reg[j].pwr_on_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg,reg_value);
}
if(cfg[i].auto_shutdown != NO_USED) {
if(cfg[i].auto_shutdown == LP_EN) {//auto_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].auto_shutdown_bitmsk);
}
else if(cfg[i].auto_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].auto_shutdown_bitmsk);
}
}
if(cfg[i].force_shutdown != NO_USED) {
if(cfg[i].force_shutdown == LP_EN) {//force_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].force_shutdown_bitmsk);
}
else if(cfg[i].force_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].force_shutdown_bitmsk);
}
}
if(cfg[i].debug_shutdown != NO_USED) {
if(cfg[i].debug_shutdown == LP_EN) {//debug_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].debug_shutdown_bitmsk);
}
else if(cfg[i].debug_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~(pd_reg[j].debug_shutdown_bitmsk));
}
}
}
++i;
}
}
/* pll */
static void pll_xtl_with_sys_config(struct pll_cfg *cfg, struct pll_reg_bit *pll_reg)
{
/*enable all xtl for simply config. xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
unsigned int i = 0, j;
unsigned int sel_mode = 0, sel_tmp = 0;
if ((!cfg) || (cfg[0].pll_id == RESERVED_NUM) || (pll_reg == NULL)) {
return;
}
/*collecting the current system mode, like TD only ..etc.*/
while (cfg[i].pll_id != RESERVED_NUM) {
j = 0;
while (pll_reg[j].pll_id != RESERVED_NUM) {
if (cfg[i].pll_id == pll_reg[j].pll_id) {
break;
}
++j;
}
/* set xtl ref */
if (pll_reg[j].cgm_ap_reg != -1) {
if (cfg[i].cgm_ap_en != NO_USED) {
if (cfg[i].cgm_ap_en == LP_EN) {
CHIP_REG_OR(pll_reg[j].cgm_ap_reg, pll_reg[j].cgm_ap_reg_bitmsk);
}
else if (cfg[i].cgm_ap_en == LP_DIS){
CHIP_REG_AND(pll_reg[j].cgm_ap_reg, ~(pll_reg[j].cgm_ap_reg_bitmsk));
}
}
}
sel_mode = 0;
/* set select by ap,cp0,cp1,cp2 */
if (pll_reg[j].pll_sys_reg != -1) {
if(cfg[i].sys != NO_USED) {
if (cfg[i].sys & AP_SYS) {
sel_mode |= BIT(0);
}
if (cfg[i].sys & CP0_SYS) {
sel_mode |= BIT(1);
}
if (cfg[i].sys & CP1_SYS) {
sel_mode |= BIT(2);
}
if (cfg[i].sys & CP2_SYS) {
sel_mode |= BIT(3);
}
if (cfg[i].sys & REF_SYS) {
sel_mode |= BIT(4);
}
sel_tmp = CHIP_REG_GET(pll_reg[j].pll_sys_reg);
sel_tmp &= ~pll_reg[j].pll_sys_reg_bitmsk;
sel_tmp |= (sel_mode << __ffs(pll_reg[j].pll_sys_reg_bitmsk)
& pll_reg[j].pll_sys_reg_bitmsk);
CHIP_REG_SET(pll_reg[j].pll_sys_reg, sel_tmp);
}
}
if (pll_reg[j].pll_wait_reg != -1) {
if (cfg[i].wait != NO_USED) {
sel_mode = cfg[i].wait << __ffs(pll_reg[j].pll_wait_reg_bitmsk);
sel_mode &= pll_reg[j].pll_wait_reg_bitmsk;
sel_tmp = CHIP_REG_GET(pll_reg[j].pll_wait_reg);
sel_tmp &= ~pll_reg[j].pll_wait_reg_bitmsk;
sel_tmp |= sel_mode;
CHIP_REG_SET(pll_reg[j].pll_wait_reg, sel_tmp);
}
}
++i;
}
}
PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
{
CHIP_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
}
