PUBLIC ERR_I2C_E I2C_Init(uint32 freq)
{
/*SC8810 use IIC1 for sensor init, but befoe SC8810 all chip use
IIC0 for sensor init. IIC1 use bit29 for Clock enable.
*/
volatile I2C_CTL_REG_T *ptr = (volatile I2C_CTL_REG_T *)I2C_BASE;
freq*=1000;
SCI_ASSERT (freq > 0);
g_wait_i2c_int_flag = TRUE;
g_i2c_open_flag=TRUE;
// gen0, enable i2c device.
#ifdef CONFIG_SC8830
#else
CHIP_REG_OR(GR_GEN0, GEN0_I2C_EN); //GEN0_I2C0_EN
#endif
ptr->rst = BIT_0;//why reset
ptr->ctl &= ~(I2CCTL_EN);//you must first disable i2c module then change clock
ptr->ctl &= ~(I2CCTL_IE);
ptr->ctl &= ~(I2CCTL_CMDBUF_EN);
I2C_SetSCLclk(freq);
CHIP_REG_OR(I2C_CTL, (I2CCTL_IE | I2CCTL_EN));
//Clear I2C int
CHIP_REG_OR(I2C_CMD, I2CCMD_INT_ACK);
return ERR_I2C_NONE;
}
static void ZipDec_Restart(void)
{
CHIP_REG_AND(ZIPDEC_CTRL , ~ZIPDEC_EN);
ZipDec_Disable();
udelay(100);
ZipDec_Enable();
ZipDec_Reset();
CHIP_REG_OR(ZIPDEC_CTRL , ZIPDEC_EN);
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_QueueEn();
}
if(zipdec_param.wait_mode==ZIPDEC_WAIT_INT)
{
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_IntEn(ZIPDEC_QUEUE_DONE_INT);
}
else
{
ZipDec_IntEn(ZIPDEC_DONE_INT);
}
ZipDec_IntEn(ZIPDEC_TIMEOUT_INT);
}
}
PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
{
// Reset the analog die register
ANA_REG_AND (ANA_HWRST_STATUS, ~0xFFF);
ANA_REG_OR (ANA_HWRST_STATUS, (val&0xFFF));
// Reset the HW_RST
CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
}
PUBLIC void I2C_Handler(uint32 param)
{
param = param; // avoid compiler warning
/* set i2c flag */
g_wait_i2c_int_flag = FALSE;
while((*(volatile uint32*)(I2C_CMD)) & I2CCMD_BUS);
/* clear i2c int */
CHIP_REG_OR(I2C_CMD, I2CCMD_INT_ACK);
}
PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
{
if(TYPE_RESET == type)
{
// Switch IRAM from DCAM to ARM
REG32 (AHB_CTL1) |= BIT_0;
CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
}
else
{
//wrong type, TODO
}
}
static int __init ZipDec_Init(void)
{
printk("%s\r\n", __func__);
ZipDec_Enable();
//ZipDec_Reset();
CHIP_REG_OR(ZIPDEC_CTRL , ZIPDEC_EN);
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_QueueEn();
}
if(zipdec_param.wait_mode==ZIPDEC_WAIT_INT)
{
if(zipdec_param.work_mode==ZIPDEC_QUEUE)
{
ZipDec_IntEn(ZIPDEC_QUEUE_DONE_INT);
ZipDec_RegCallback(ZIPDEC_QUEUE_DONE_INT,ZipDec_Callback_QueueDone);
}
else
{
ZipDec_IntEn(ZIPDEC_DONE_INT);
ZipDec_RegCallback(ZIPDEC_DONE_INT,ZipDec_Callback_Done);
}
ZipDec_IntEn(ZIPDEC_TIMEOUT_INT);
ZipDec_RegCallback(ZIPDEC_TIMEOUT_INT,ZipDec_Callback_Timeout);
if(request_irq( zipdec_param.int_num,ZipDec_IsrHandler,0,"zip dec",0))
{
printk("zip dec request irq error\n");
return-1;
}
}
_lzo1x_decompress_safe = (zipdec_param.work_mode==ZIPDEC_QUEUE) ? (_lzo1x_decompress_queue) : (_lzo1x_decompress_single);
Zip_Dec_Wait=(zipdec_param.wait_mode==ZIPDEC_WAIT_INT)? Zip_Dec_Wait_Int : Zip_Dec_Wait_Pool;
ZipDec_decompress = get_zip_type() ? lzo1x_decompress_safe_hw : lzo1x_decompress_safe;
//ZipDec_Set_Timeout(zipdec_param.timeout);
return 0;
}
int lzo1x_decompress_safe_hw(const unsigned char *src , size_t src_len , unsigned char *dst , size_t *dst_len)
{
volatile uint32_t dec_len;
uint32_t src_addr =(uint32_t)src;
uint32_t dst_addr =(uint32_t)dst;
if (!dst || !dst_len || !src || !src_len ||(src_len > PAGE_SIZE)) return LZO_HW_IN_PARA_ERROR;
//printk("lzo hw decompress\r\n");
CHIP_REG_OR(ZIPDEC_CTRL , ZIPDEC_EN);
if(_lzo1x_decompress_safe((uint32_t)src_addr ,src_len , dst_addr ,&dec_len))
{
*dst_len = dec_len;
ZipDec_Restart();
return LZO_HW_ERROR;
}
*dst_len = ZIP_WORK_LENGTH;
return LZO_HW_OK;
}
static void pd_shutdown_config(struct shutdown_cfg *cfg,
struct pd_reg_bit *pd_reg)
{
/*enable all xtl for simply config. xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
unsigned int i = 0, j;
unsigned int reg_value = 0;
if ((!cfg) || (cfg[0].pd_shutdown_id == RESERVED_NUM) || (pd_reg == NULL)) {
return;
}
/*collecting the current system mode, like TD only ..etc.*/
while (cfg[i].pd_shutdown_id != RESERVED_NUM) {
j = 0;
while (pd_reg[j].pd_shutdown_id != RESERVED_NUM) {
if (cfg[i].pd_shutdown_id == pd_reg[j].pd_shutdown_id) {
break;
}
++j;
}
if (pd_reg[j].pd_shutdown_id == RESERVED_NUM) {
continue;
}
if (pd_reg[j].pd_reg != -1) {
if(cfg[i].iso_on_delay != NO_USED) {
reg_value = cfg[i].iso_on_delay << __ffs(pd_reg[j].iso_on_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].iso_on_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
}
if(cfg[i].pwr_on_seq_delay != NO_USED) {//pwr_on_seq_delay
reg_value = cfg[i].pwr_on_seq_delay
<< __ffs(pd_reg[j].pwr_on_seq_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_seq_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg, reg_value);
}
if(cfg[i].pwr_on_delay != NO_USED) {//pwr_on_delay
reg_value = cfg[i].pwr_on_delay << __ffs(pd_reg[j].pwr_on_delay_bitmsk);
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].pwr_on_delay_bitmsk);
CHIP_REG_OR(pd_reg[j].pd_reg,reg_value);
}
if(cfg[i].auto_shutdown != NO_USED) {
if(cfg[i].auto_shutdown == LP_EN) {//auto_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].auto_shutdown_bitmsk);
}
else if(cfg[i].auto_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].auto_shutdown_bitmsk);
}
}
if(cfg[i].force_shutdown != NO_USED) {
if(cfg[i].force_shutdown == LP_EN) {//force_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].force_shutdown_bitmsk);
}
else if(cfg[i].force_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~pd_reg[j].force_shutdown_bitmsk);
}
}
if(cfg[i].debug_shutdown != NO_USED) {
if(cfg[i].debug_shutdown == LP_EN) {//debug_shutdown
CHIP_REG_OR(pd_reg[j].pd_reg, pd_reg[j].debug_shutdown_bitmsk);
}
else if(cfg[i].debug_shutdown == LP_DIS) {
CHIP_REG_AND(pd_reg[j].pd_reg, ~(pd_reg[j].debug_shutdown_bitmsk));
}
}
}
++i;
}
}
/* pll */
static void pll_xtl_with_sys_config(struct pll_cfg *cfg, struct pll_reg_bit *pll_reg)
{
/*enable all xtl for simply config. xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/
unsigned int i = 0, j;
unsigned int sel_mode = 0, sel_tmp = 0;
if ((!cfg) || (cfg[0].pll_id == RESERVED_NUM) || (pll_reg == NULL)) {
return;
}
/*collecting the current system mode, like TD only ..etc.*/
while (cfg[i].pll_id != RESERVED_NUM) {
j = 0;
while (pll_reg[j].pll_id != RESERVED_NUM) {
if (cfg[i].pll_id == pll_reg[j].pll_id) {
break;
}
++j;
}
/* set xtl ref */
if (pll_reg[j].cgm_ap_reg != -1) {
if (cfg[i].cgm_ap_en != NO_USED) {
if (cfg[i].cgm_ap_en == LP_EN) {
CHIP_REG_OR(pll_reg[j].cgm_ap_reg, pll_reg[j].cgm_ap_reg_bitmsk);
}
else if (cfg[i].cgm_ap_en == LP_DIS){
CHIP_REG_AND(pll_reg[j].cgm_ap_reg, ~(pll_reg[j].cgm_ap_reg_bitmsk));
}
}
}
sel_mode = 0;
/* set select by ap,cp0,cp1,cp2 */
if (pll_reg[j].pll_sys_reg != -1) {
if(cfg[i].sys != NO_USED) {
if (cfg[i].sys & AP_SYS) {
sel_mode |= BIT(0);
}
if (cfg[i].sys & CP0_SYS) {
sel_mode |= BIT(1);
}
if (cfg[i].sys & CP1_SYS) {
sel_mode |= BIT(2);
}
if (cfg[i].sys & CP2_SYS) {
sel_mode |= BIT(3);
}
if (cfg[i].sys & REF_SYS) {
sel_mode |= BIT(4);
}
sel_tmp = CHIP_REG_GET(pll_reg[j].pll_sys_reg);
sel_tmp &= ~pll_reg[j].pll_sys_reg_bitmsk;
sel_tmp |= (sel_mode << __ffs(pll_reg[j].pll_sys_reg_bitmsk)
& pll_reg[j].pll_sys_reg_bitmsk);
CHIP_REG_SET(pll_reg[j].pll_sys_reg, sel_tmp);
}
}
if (pll_reg[j].pll_wait_reg != -1) {
if (cfg[i].wait != NO_USED) {
sel_mode = cfg[i].wait << __ffs(pll_reg[j].pll_wait_reg_bitmsk);
sel_mode &= pll_reg[j].pll_wait_reg_bitmsk;
sel_tmp = CHIP_REG_GET(pll_reg[j].pll_wait_reg);
sel_tmp &= ~pll_reg[j].pll_wait_reg_bitmsk;
sel_tmp |= sel_mode;
CHIP_REG_SET(pll_reg[j].pll_wait_reg, sel_tmp);
}
}
++i;
}
}
PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
{
CHIP_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
}
