void SAMA5D3X_ClockInit() { PMC_SelectExt12M_Osc(); PMC_SwitchMck2Main(); PMC_SetPllA(CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_PLLACOUNT(0x3F) | CKGR_PLLAR_OUTA(0x0) | CKGR_PLLAR_MULA(65) | CKGR_PLLAR_DIVA(1), 0x3u << 8); PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2); PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK); PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3); PMC_SwitchMck2Pll(); }
/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { uint8_t i; uint32_t _dwTimeout = 0; volatile uint32_t read = 0; if ((uint32_t)LowLevelInit < EBI_CS0_ADDR) /* Code not in external mem */ { /* Switch to PLL + prescaler */ read = PMC->PMC_MCKR; read &= ~(PMC_MCKR_CSS_Msk); read |= PMC_MCKR_CSS_MAIN_CLK; PMC->PMC_MCKR = read; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(64) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; _dwTimeout = 0; while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (_dwTimeout++ < CLOCK_TIMEOUT)); PMC->CKGR_PLLAR = 0; /* Initialize PLLA */ PMC->CKGR_PLLAR = CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(199) | CKGR_PLLAR_OUTA(0) | CKGR_PLLAR_PLLACOUNT(63) | CKGR_PLLAR_DIVA(3); _dwTimeout = 0; while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (_dwTimeout++ < CLOCK_TIMEOUT)); /* Wait for the master clock if it was already initialized */ for ( _dwTimeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; ); /* Switch to fast clock **********************/ /* Switch to main oscillator + prescaler */ read = PMC->PMC_MCKR; read &= ~(PMC_MCKR_MDIV_Msk); read |= (PMC_MCKR_MDIV_PCK_DIV3 | PMC_MCKR_PLLADIV2_DIV2); PMC->PMC_MCKR = read; /* Wait for the master clock if it was already initialized */ for ( _dwTimeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; ); /* Switch to main oscillator + prescaler */ read = PMC->PMC_MCKR; read &= ~(PMC_MCKR_PRES_Msk); read |= PMC_MCKR_PRES_CLOCK; PMC->PMC_MCKR = read; /* Wait for the master clock if it was already initialized */ for ( _dwTimeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; ); /* Switch to PLL + prescaler */ read = PMC->PMC_MCKR; read &= ~(PMC_MCKR_CSS_Msk); read |= PMC_MCKR_CSS_PLLA_CLK; PMC->PMC_MCKR = read; /* Wait for the master clock if it was already initialized */ for ( _dwTimeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (_dwTimeout++ < CLOCK_TIMEOUT) ; ); } /* Initialize AIC */ AIC->AIC_IDCR = 0xFFFFFFFF; AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler; for (i = 1; i < 31; i++) { AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler; } AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; /* Unstack nested interrupts */ for (i = 0; i < 8 ; i++) { AIC->AIC_EOICR = 0; } /* Remap */ BOARD_RemapRam(); BOARD_ConfigureDdram(); }
/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { uint32_t i; if ((uint32_t)LowLevelInit < DDR_CS_ADDR) /* Code not in external mem */ { PMC_SelectExt12M_Osc(); PMC_SwitchMck2Main(); PMC_SetPllA( CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_PLLACOUNT(0x3F) | CKGR_PLLAR_OUTA(0x0) | CKGR_PLLAR_MULA(65) | CKGR_PLLAR_DIVA(1), 0x3u << 8); PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2); PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK); PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3); PMC_SwitchMck2Pll(); } #if 0 uint32_t abcdsr; /* Configure PCK1 to measure MCK */ PIOD->PIO_IDR = (1<<31); abcdsr = PIOD->PIO_ABCDSR[0]; PIOD->PIO_ABCDSR[0] = ((1<<31) | abcdsr); abcdsr = PIOD->PIO_ABCDSR[1]; PIOD->PIO_ABCDSR[1] &= (~(1<<31) & abcdsr); PIOD->PIO_PDR = (1<<31); /* Disable programmable clock 1 output */ REG_PMC_SCDR = PMC_SCER_PCK1; /* Enable the DAC master clock */ PMC->PMC_PCK[1] = PMC_PCK_CSS_MCK_CLK | PMC_PCK_PRES_CLOCK; /* Enable programmable clock 1 output */ REG_PMC_SCER = PMC_SCER_PCK1; /* Wait for the PCKRDY1 bit to be set in the PMC_SR register*/ while ((REG_PMC_SR & PMC_SR_PCKRDY1) == 0); #endif /* select FIQ */ AIC->AIC_SSR = 0; AIC->AIC_SVR = (unsigned int) defaultFiqHandler; for (i = 1; i < 31; i++) { AIC->AIC_SSR = i; AIC->AIC_SVR = (unsigned int) defaultIrqHandler; } AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; /* Disable all interrupts */ for (i = 1; i < 31; i++) { AIC->AIC_SSR = i; AIC->AIC_IDCR = 1 ; } /* Clear All pending interrupts flags */ for (i = 1; i < 31; i++) { AIC->AIC_SSR = i; AIC->AIC_ICCR = 1 ; } /* Perform 8 IT acknoledge (write any value in EOICR) */ for (i = 0; i < 8 ; i++) { AIC->AIC_EOICR = 0; } /* Remap */ BOARD_RemapRam(); }