void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184 MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to Internal RC and set HCLK divider to 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable external XTAL 12 MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set Flash Access Delay */ FMC->FTCTL |= FMC_FTCTL_FOM_Msk; /* Set core clock */ CLK_SetCoreClock(72000000); /* Enable module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(UART1_MODULE); CLK_EnableModuleClock(USBD_MODULE); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3)); /* Enable USB LDO33 */ SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPD multi-function pins for UART0 RXD, TXD and Clock Output */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_CLKO; /* Set GPA multi-function pins for UART1 RXD and TXD */ SYS->GPA_MFPL = SYS_GPA_MFPL_PA0MFP_UART1_TXD | SYS_GPA_MFPL_PA1MFP_UART1_RXD; /* Enable CLKO (PD.6) for monitor HCLK. CLKO = HCLK/8 Hz */ CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(UART1_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Set PB multi-function pins for UART1 RXD(PB.2), TXD(PB.3) and nCTS(PB.4) */ SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB2MFP_UART1_RXD | SYS_GPB_MFPL_PB3MFP_UART1_TXD | SYS_GPB_MFPL_PB4MFP_UART1_nCTS); /* Set PB multi-function pins for UART1 nRTS(PB.8) */ SYS->GPB_MFPH &= (~SYS_GPB_MFPH_PB8MFP_Msk); SYS->GPB_MFPH |= SYS_GPB_MFPH_PB8MFP_UART1_nRTS; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(TMR0_MODULE); CLK_EnableModuleClock(SPI0_MODULE); CLK_EnableModuleClock(SPI1_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ; /* SPI0: GPE4=SS0, GPE3=MOSI0, GPE2=MISO0, GPE5=CLK */ SYS->GPE_MFPL = (SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 | SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 | SYS_GPE_MFPL_PE4MFP_SPI0_SS0 | SYS_GPE_MFPL_PE5MFP_SPI0_CLK); /* SPI1: GPC12=SS0, GPC15=MOSI0, GPD0=MISO0, GPD1=CLK */ SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_SPI1_SS0 | SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0); SYS->GPD_MFPL = (SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 | SYS_GPD_MFPL_PD1MFP_SPI1_CLK); /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Set HCLK source form HXT and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1)); /* Set HCLK frequency 42MHz */ CLK_SetCoreClock(42000000); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/ CLK_DisablePLL(); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /* Enable EADC module clock */ CLK_EnableModuleClock(EADC_MODULE); /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */ CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Configure the GPB0 - GPB3 ADC analog input pins. */ SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3); /* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */ GPIO_DISABLE_DIGITAL_PATH(PB, 0xF); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; /* Wait for HIRC clock ready */ while(!(CLK->STATUS & CLK_STATUS_HIRCSTB_Msk)); /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | CLK_CLKDIV0_HCLK(1); /* Set PLL to Power-down mode */ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Enable HXT clock (external XTAL 12MHz) */ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; /* Wait for HXT clock ready */ while(!(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)); /* Set core clock as PLL_CLOCK from PLL */ CLK->PLLCTL = PLLCTL_SETTING; while(!(CLK->STATUS & CLK_STATUS_PLLSTB_Msk)); CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_PLL; /* Update System Core Clock */ PllClock = PLL_CLOCK; // PLL SystemCoreClock = PLL_CLOCK / 1; // HCLK CyclesPerUs = PLL_CLOCK / 1000000; // For CLK_SysTickDelay() /* Enable UART module clock */ CLK->APBCLK0 |= CLK_APBCLK0_UART0CKEN_Msk; /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_UARTSEL_Msk)) | CLK_CLKSEL1_UARTSEL_HXT; CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_UARTDIV_Msk)) | CLK_CLKDIV0_UART(1); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Set PC multi-function pins for CLKO(PC.1) */ SYS->GPC_MFPL &= ~SYS_GPC_MFPL_PC1MFP_Msk; SYS->GPC_MFPL |= SYS_GPC_MFPL_PC1MFP_CLKO; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); /* Waiting for LIRC clock stable */ CLK_WaitClockReady( CLK_STATUS_LIRCSTB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(WDT_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ; /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(TMR0_MODULE); CLK_EnableModuleClock(SPI2_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ; /* SPI2: SS0=GPH_5, MOSI0=GPH_8, MISO0=GPH_7, CLK=GPH_6, MISO1=GPH_9, MOSI11=GPH10 */ SYS->GPH_MFPL = (SYS_GPH_MFPL_PH5MFP_SPI2_SS0 | SYS_GPH_MFPL_PH6MFP_SPI2_CLK | SYS_GPH_MFPL_PH7MFP_SPI2_MISO0); SYS->GPH_MFPH = (SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0 | SYS_GPH_MFPH_PH9MFP_SPI2_MISO1 | SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1); /* Lock protected registers */ SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCON_HXT_EN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCON |= CLK_PLLCON_PD_Msk; /* Set PLL frequency */ CLK->PLLCON = PLLCON_SETTING; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(PDMA_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_CLKDIV0_UART(1)); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1_MFP_Msk|SYS_GPG_MFPL_PG2_MFP_Msk); SYS->GPG_MFPL |= SYS_GPG_MFPL_PG1_MFP_UART0_RXD | SYS_GPG_MFPL_PG2_MFP_UART0_TXD ; /* Set GPG multi-function pins for CKO */ SYS->GPC_MFPL = (SYS->GPC_MFPL & ~SYS_GPC_MFPL_PC5_MFP_Msk) | SYS_GPC_MFPL_PC5_MFP_CLK_O ; /* Lock protected registers */ SYS_LockReg(); }
void setupCommandUART() { /* Enable peripheral clock */ CLK_EnableModuleClock(UART0_MODULE); /* Peripheral clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1)); /* Set PD multi-function pins for UART0 RXD, TXD */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD; /* Reset UART module */ SYS_ResetModule(UART0_RST); /* Configure UART0 and set UART0 Baudrate */ UART_Open(UART0, 115200); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/ CLK_DisablePLL(); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /* Enable DAC module clock */ CLK_EnableModuleClock(DAC_MODULE); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Set PB multi-function pins for DAC voltage output */ SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk; SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_DAC ; }
void setupGpsUART() { #ifdef GPS_UART /* Enable peripheral clock */ CLK_EnableModuleClock(UART1_MODULE); /* Peripheral clock source */ CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1)); /* Set PE multi-function pins for UART0 RXD, TXD */ SYS->GPE_MFPH = SYS_GPE_MFPH_PE13MFP_UART1_RXD | SYS_GPE_MFPH_PE12MFP_UART1_TXD; /* Reset UART module */ SYS_ResetModule(UART1_RST); /* Configure UART0 and set UART0 Baudrate */ UART_Open(UART1, GPS_BAUD); UART_EnableInt(UART1, UART_INTEN_RDAIEN_Msk); #endif }
void Usart_Init(void) { /* Enable IP clock */ CLK_EnableModuleClock(UART3_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC , CLK_CLKDIV0_UART(1)); /* Set GPD multi-function pins for UART3 RXD and TXD */ SYS->GPD_MFPL |= SYS_GPD_MFPL_PD4MFP_UART3_RXD | SYS_GPD_MFPL_PD5MFP_UART3_TXD ; GPIO_SetMode(PD, 5, GPIO_MODE_OUTPUT); GPIO_SetMode(PD, 4, GPIO_MODE_INPUT); UART_Open(UART3, 9600); // UART_DisableFlowCtrl(UART3); //UART_SetLine_Config(UART3, 115200, UART_WORD_LEN_8,UART_PARITY_NONE,UART_STOP_BIT_1); // UART_EnableInt(UART3, UART_INTEN_RDAIEN_Msk ); // NVIC_SetPriority(UART3_IRQn, 2 ); //NVIC_EnableIRQ(UART3_IRQn); //UART_INTEN_THREIEN_Msk NVIC_DisableIRQ(UART3_IRQn); UART_Write(UART3,"Usart3 init done!\r\n", sizeof("Usart3 init done!\r\n")); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to HIRC */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable HXT and LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_LIRCEN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk | CLK_STATUS_LIRCSTB_Msk); /* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/ CLK_SetCoreClock(PLL_CLOCK); CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2); /* Enable peripheral clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(WDT_MODULE); /* Peripheral clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_PLL, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD, TXD */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; /* Waiting for HIRC clock ready */ while(!(CLK->STATUS & CLK_STATUS_HIRCSTB_Msk)); /* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */ CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLKSEL_Msk; CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_HIRC; CLK->CLKDIV0 &= ~CLK_CLKDIV0_HCLKDIV_Msk; CLK->CLKDIV0 |= CLK_CLKDIV0_HCLK(1); /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Enable HXT clock (external XTAL 12MHz) */ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; /* Waiting for HXT clock ready */ while(!(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)); /* Set core clock as PLL_CLOCK from PLL */ CLK->PLLCTL = PLLCTL_SETTING; while(!(CLK->STATUS & CLK_STATUS_PLLSTB_Msk)); CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLKSEL_Msk); CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_PLL; /* Update system core clock */ PllClock = PLL_CLOCK; // PLL SystemCoreClock = PLL_CLOCK / 1; // HCLK CyclesPerUs = PLL_CLOCK / 1000000; // For CLK_SysTickDelay() /* Enable UART module clock */ CLK->APBCLK0 |= CLK_APBCLK0_UART0CKEN_Msk; /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK->CLKSEL1 &= ~CLK_CLKSEL1_UARTSEL_Msk; CLK->CLKSEL1 |= CLK_CLKSEL1_UARTSEL_HXT; CLK->CLKDIV0 &= ~CLK_CLKDIV0_UARTDIV_Msk; CLK->CLKDIV0 |= CLK_CLKDIV0_UART(1); /* Enable PWM0 module clock */ CLK->APBCLK1 |= CLK_APBCLK1_PWM0CKEN_Msk; /* Select PWM0 module clock source as PLL */ CLK->CLKSEL2 &= ~CLK_CLKSEL2_PWM0SEL_Msk; CLK->CLKSEL2 |= CLK_CLKSEL2_PWM0SEL_PLL; /* Enable DAC module clock */ CLK->APBCLK1 |= CLK_APBCLK1_DACCKEN_Msk; /* Enable PDMA module clock */ CLK->AHBCLK |= CLK_AHBCLK_PDMACKEN_Msk; /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Set PB multi-function pins for DAC voltage output */ SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk; SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_DAC; /* Set PC multi-function pins for PWMA Channel0 */ SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC0MFP_Msk)); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Switch HCLK clock source to XTAL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = PLLCTL_SETTING; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLKSEL_Msk); CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_PLL; /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */ SystemCoreClockUpdate(); PllClock = PLL_CLOCK; // PLL SystemCoreClock = PLL_CLOCK / 2; // HCLK CyclesPerUs = SystemCoreClock / 1000000; // For SYS_SysTickDelay() /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /*---------------------------------------------------------------------------------------------------------*/ /* Init USB Host clock */ /*---------------------------------------------------------------------------------------------------------*/ // Configure OTG function as Host-Only SYS->USBPHY = 0x101; #ifdef AUTO_POWER_CONTROL /* Below settings is use power switch IC to enable/disable USB Host power. Set PC.4 is VBUS_EN function pin and PC.3 VBUS_ST function pin */ //SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk); //SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST | SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN); /* Below settings is use power switch IC to enable/disable USB Host power. Set PA.2 is VBUS_EN function pin and PA.3 VBUS_ST function pin */ SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk); SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST | SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN); CLK->APBCLK0 |= CLK_APBCLK0_OTGCKEN_Msk; //Enable OTG_EN clock #else /* Below settings is use GPIO to enable/disable USB Host power. Set PC.4 output high to enable USB power */ SYS->GPC_MFPL &= ~SYS_GPC_MFPL_PC4MFP_Msk; PC->MODE = (PC->MODE & ~GPIO_MODE_MODE4_Msk) | (0x1 << GPIO_MODE_MODE4_Pos); PC->DOUT |= 0x10; #endif // USB clock divided by 2 CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_USBDIV_Msk) | (1 << CLK_CLKDIV0_USBDIV_Pos); // Enable USB Host CLK->AHBCLK |= CLK_AHBCLK_USBHCKEN_Msk; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Waiting for PLL clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Enable PWM0 module clock */ CLK_EnableModuleClock(PWM0_MODULE); /*---------------------------------------------------------------------------------------------------------*/ /* PWM clock frequency configuration */ /*---------------------------------------------------------------------------------------------------------*/ /* Select HCLK clock source as PLL and and HCLK clock divider as 2 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2)); /* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */ /* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */ CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, NULL); /* case 2.PWM clock frequency is set double to HCLK: select PWM module clock source as PLL */ //CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PLL, NULL); /*---------------------------------------------------------------------------------------------------------*/ /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /* Reset PWM0 module */ SYS_ResetModule(PWM0_RST); /* Update System Core Clock */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Set PC multi-function pins for PWM0 Channel0~3 */ SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC0MFP_Msk)); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0; SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC1MFP_Msk)); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC1MFP_PWM0_CH1; SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC2MFP_Msk)); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC2MFP_PWM0_CH2; SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC3MFP_Msk)); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC3MFP_PWM0_CH3; }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCON_HXT_EN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady( CLK_CLKSTATUS_HXT_STB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCON|= CLK_PLLCON_PD_Msk; /* Set PLL frequency */ CLK->PLLCON = PLLCON_SETTING; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); /* enable PWM0 Channel 0~5 peripheral clock */ CLK_EnableModuleClock(PWM0CH01_MODULE); CLK_EnableModuleClock(PWM0CH23_MODULE); CLK_EnableModuleClock(PWM0CH45_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_CLKDIV0_UART(1)); /* Set PCLK as PWM0 channel 0~3 clock source */ CLK_SetModuleClock(PWM0CH01_MODULE,CLK_CLKSEL2_PWM0CH01_S_PCLK,1); CLK_SetModuleClock(PWM0CH23_MODULE,CLK_CLKSEL2_PWM0CH23_S_PCLK,1); CLK_SetModuleClock(PWM0CH45_MODULE,CLK_CLKSEL2_PWM0CH45_S_PCLK,1); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL = SYS_GPG_MFPL_PG1_MFP_UART0_RXD | SYS_GPG_MFPL_PG2_MFP_UART0_TXD ; /* Set GPG multi-function pins for CKO */ SYS->GPC_MFPL = (SYS->GPC_MFPL & ~SYS_GPC_MFPL_PC5_MFP_Msk) | SYS_GPC_MFPL_PC5_MFP_CLK_O ; /* Set A5 A6 C10 C11 A12 A11 multi-function pins for PWM Channel 0~5 */ SYS->GPA_MFPL = (SYS->GPA_MFPL & ~(SYS_GPA_MFPL_PA5_MFP_Msk | SYS_GPA_MFPL_PA6_MFP_Msk)) | SYS_GPA_MFPL_PA5_MFP_PWM0_CH0 | SYS_GPA_MFPL_PA6_MFP_PWM0_CH1; SYS->GPC_MFPH = (SYS->GPC_MFPH & ~(SYS_GPC_MFPH_PC10_MFP_Msk | SYS_GPC_MFPH_PC11_MFP_Msk)) | SYS_GPC_MFPH_PC10_MFP_PWM0_CH2 | SYS_GPC_MFPH_PC11_MFP_PWM0_CH3; SYS->GPA_MFPH = (SYS->GPA_MFPH & ~(SYS_GPA_MFPH_PA12_MFP_Msk | SYS_GPA_MFPH_PA11_MFP_Msk)) | SYS_GPA_MFPH_PA12_MFP_PWM0_CH4 | SYS_GPA_MFPH_PA11_MFP_PWM0_CH5; /* Lock protected registers */ SYS_LockReg(); }
void VCOM_LineCoding(uint8_t port) { uint32_t u32Reg, u32Tmp, u32Baudrate, u32SysTmp; uint32_t u32Div = 0; if(port == 0) { u32Baudrate = gLineCoding.u32DTERate; u32Tmp = 65 * u32Baudrate; u32SysTmp = PllClock / 1000; /* Check we need to divide PLL clock. Note: It may not work when baudrate is very small,e.g. 110 bps */ if(u32SysTmp > u32Tmp) u32Div = u32SysTmp / u32Tmp; /* Update UART peripheral clock frequency. */ u32SysTmp = PllClock / (u32Div + 1); // Reset software fifo comRbytes = 0; comRhead = 0; comRtail = 0; comTbytes = 0; comThead = 0; comTtail = 0; // Reset hardware fifo UART0->FIFO = 0x6; // Set baudrate, clock source and clock divider UART0->BAUD = 0x30000000 + ((u32SysTmp + gLineCoding.u32DTERate / 2) / gLineCoding.u32DTERate - 2); CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_PLL, CLK_CLKDIV0_UART(u32Div + 1)); // Set parity if(gLineCoding.u8ParityType == 0) u32Reg = 0; // none parity else if(gLineCoding.u8ParityType == 1) u32Reg = 0x08; // odd parity else if(gLineCoding.u8ParityType == 2) u32Reg = 0x18; // even parity else u32Reg = 0; /* bit width */ switch(gLineCoding.u8DataBits) { case 5: u32Reg |= 0; break; case 6: u32Reg |= 1; break; case 7: u32Reg |= 2; break; case 8: u32Reg |= 3; break; default: break; } /* stop bit */ if(gLineCoding.u8CharFormat > 0) u32Reg |= 0x4; // 2 or 1.5 bits UART0->LINE = u32Reg; } }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set Flash Access Delay */ FMC->FTCTL |= FMC_FTCTL_FOM_Msk; /* Set core clock */ CLK_SetCoreClock(72000000); /* Enable module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(USBD_MODULE); CLK_EnableModuleClock(TMR0_MODULE); CLK_EnableModuleClock(I2C0_MODULE); CLK_EnableModuleClock(SPI1_MODULE); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3)); CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0); CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PLL, 0); /* Enable USB LDO33 */ SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD.0, PD.1, PD.6, PD.4 and PD.5 as SPI1_I2SMCLK, UART0 TXD, UART0 RXD, I2C0_SDA and I2C0_SCL function pins */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_UART0_RXD | SYS_GPD_MFPL_PD4MFP_I2C0_SDA | SYS_GPD_MFPL_PD5MFP_I2C0_SCL; /* Set I2S1 interface: I2S1_LRCLK (PA.4), I2S1_DO (PA.5), I2S1_DI (PA.6), I2S1_BCLK (PA.7) */ SYS->GPA_MFPL = SYS_GPA_MFPL_PA4MFP_SPI1_SS | SYS_GPA_MFPL_PA5MFP_SPI1_MOSI | SYS_GPA_MFPL_PA6MFP_SPI1_MISO | SYS_GPA_MFPL_PA7MFP_SPI1_CLK; /* Set PC.1 as CLKO pin */ SYS->GPC_MFPL = SYS_GPC_MFPL_PC1MFP_CLKO; /* Enable CLKO (PC.1) for monitor HCLK. CLKO = HCLK/8 Hz */ CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0); }
//========================================================================= //----- (0000652C) -------------------------------------------------------- void InitDevices() { SYS_UnlockReg(); // Internal 22.1184MHz oscillator CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk ); CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk ); CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK( 1 ) ); // 12.000MHz external crystal CLK_EnableXtalRC( CLK_PWRCTL_HXTEN_Msk ); CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk ); // FMC Frequency Optimisation mode <= 72MHz FMC_EnableFreqOptimizeMode( FMC_FTCTL_OPTIMIZE_72MHZ ); // Setup PLL to 144MHz and HCLK source to PLL/2 CLK_SetCoreClock( CPU_FREQ ); // UART0 CLK = HXT/1 #if (ENABLE_UART) CLK_EnableModuleClock( UART0_MODULE ); CLK_SetModuleClock( UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART( 1 ) ); #endif // USB CLK = PLL/3 (48MHz) CLK_EnableModuleClock( USBD_MODULE ); CLK_SetModuleClock( USBD_MODULE, 0, CLK_CLKDIV0_USB( 3 ) ); SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; // WDT CLK = LIRC/1 CLK_EnableModuleClock( WDT_MODULE ); CLK_SetModuleClock( WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0 ); // SPI0 CLK = PCLK0/1 CLK_EnableModuleClock( SPI0_MODULE ); // EADC CLK = PCLK1/8 (9MHz) CLK_EnableModuleClock( EADC_MODULE ); CLK_SetModuleClock( EADC_MODULE, 0, CLK_CLKDIV0_EADC( 8 ) ); // CRC CLK = HCLK/1 CLK_EnableModuleClock( CRC_MODULE ); // TIMERS CLOCKS CLK_EnableModuleClock( TMR0_MODULE ); CLK_EnableModuleClock( TMR1_MODULE ); CLK_EnableModuleClock( TMR2_MODULE ); CLK_EnableModuleClock( TMR3_MODULE ); CLK_SetModuleClock( TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0 ); CLK_SetModuleClock( TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0 ); CLK_SetModuleClock( TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HIRC, 0 ); CLK_SetModuleClock( TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, 0 ); // Enable battery voltage sampling by ADC SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk; // ADC reference voltage SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V; // Brown-out detector; interrupts under 2.2V SYS_EnableBOD( SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V ); // Update clock data SystemCoreClockUpdate(); WDT_Open( WDT_TIMEOUT_2POW18, WDT_RESET_DELAY_18CLK, TRUE, FALSE ); SYS_LockReg(); }
static void prvSetupHardware( void ) { /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for 12MHz clock ready */ CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(EMAC_MODULE); /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); // Configure MDC clock rate to HCLK / (127 + 1) = 656 kHz if system is running at 84 MHz CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127)); /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPG multi-function pins for UART0 RXD and TXD */ SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ; // Configure RMII pins SYS->GPC_MFPL = SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK | SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR | SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV | SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 | SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 | SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 | SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1; SYS->GPC_MFPH = SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN; // Enable high slew rate on all RMII pins PC->SLEWCTL |= 0x1DF; // Configure MDC, MDIO at PB14 & PB15 SYS->GPB_MFPH = SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO; /* Lock protected registers */ SYS_LockReg(); /* Init UART to 115200-8n1 for print message */ UART_Open(UART0, 115200); }