void SYS_PLL_Demo(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* PLL clock configuration test */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n-------------------------[ Test PLL ]-----------------------------\n");
for(i = 0; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[0]) ; i++)
{
/* Select HCLK clock source from PLL.
PLL will be configured to twice specified frequency.
And HCLK clock source divider will be set to 2.
*/
CLK_SetCoreClock(g_au32PllSetting[i]);
printf("%d Change system clock to %d Hz ...................... ",i,SystemCoreClock);
/* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
CLK_EnableCKO(CLK_CLKSEL2_CLKOSEL_HCLK, 1, 0);
/* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000);
printf("[OK]\n");
/* Disable CLKO clock */
CLK_DisableCKO();
}
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to Internal RC and set HCLK divider to 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable external XTAL 12 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set Flash Access Delay */
FMC->FTCTL |= FMC_FTCTL_FOM_Msk;
/* Set core clock */
CLK_SetCoreClock(72000000);
/* Enable module clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(UART1_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
/* Select module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
/* Enable USB LDO33 */
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPD multi-function pins for UART0 RXD, TXD and Clock Output */
SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_CLKO;
/* Set GPA multi-function pins for UART1 RXD and TXD */
SYS->GPA_MFPL = SYS_GPA_MFPL_PA0MFP_UART1_TXD | SYS_GPA_MFPL_PA1MFP_UART1_RXD;
/* Enable CLKO (PD.6) for monitor HCLK. CLKO = HCLK/8 Hz */
CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0);
}
void SYS_PLL_Test(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* PLL clock configuration test */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n-------------------------[ Test PLL ]-----------------------------\n");
for(i = 0; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[0]) ; i++) {
/* Switch HCLK clock source to HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */
CLK_DisablePLL();
/* Set PLL frequency */
CLK->PLLCON = g_au32PllSetting[i];
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
printf(" Change system clock to %d Hz ...................... ", SystemCoreClock);
/* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK, 1, 0);
/* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000);
if(pi()) {
printf("[FAIL]\n");
} else {
printf("[OK]\n");
}
/* Disable CKO clock */
CLK_DisableCKO();
}
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main (void)
{
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Init UART for printf */
UART_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
printf("+----------------------------------------+\n");
printf("| Mini58 System Driver Sample Code |\n");
printf("+----------------------------------------+\n");
/* Unlock protected registers before setting Brown-out detector function and Power-down mode */
SYS_UnlockReg();
/* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
CLK_EnableCKO(CLK_CLKSEL2_CLKOSEL_HCLK, 1, 0);
/* Enable Brown-out detector function */
SYS_ENABLE_BOD();
/* Set Brown-out detector voltage level as 2.7V */
SYS_SET_BOD_LEVEL(SYS_BODCTL_BODVL_2_7V);
/* Enable Brown-out detector interrupt function */
SYS_DISABLE_BOD_RST();
/* Enable Brown-out detector and Power-down wake-up interrupt */
NVIC_EnableIRQ(BOD_IRQn);
NVIC_EnableIRQ(PDWU_IRQn);
printf("System enter to Power-down mode.\n");
printf("System wake-up if VDD voltage is lower than 2.7V.\n\n");
/* Enter to Power-down mode */
PowerDownFunction();
/* Wait for Power-down mode wake-up interrupt happen */
while(1);
}
int32_t main (void)
{
uint32_t u32data;
/* HCLK will be set to 42MHz in SYS_Init(void)*/
if(SYS->RegLockAddr == 1) // In end of main function, program issued CPU reset and write-protection will be disabled.
SYS_LockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+----------------------------------------+\n");
printf("| Nano100 System Driver Sample Code |\n");
printf("+----------------------------------------+\n");
if (M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
GetChar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector and power down settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if (SYS->RegLockAddr != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.5V ,
Enable Brown-Out Interrupt function */
SYS_EnableBOD(SYS_BODCTL_BOD25_INT_EN_Msk,SYS_BODCTL_BOD25_EN_Msk);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Waiting for message send out */
// _UART_WAIT_TX_EMPTY(UART0);
/* Enable CKO and output frequency = system clock / 4 */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK,1);
/* Switch HCLK clock source to Internal 11.0592MHz */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1));
/* Enable WDT clock */
CLK_EnableModuleClock(WDT_MODULE);
/* Enable WDT and interrupt */
WDT->CTL = 0x00000050 | 0x00000004 | 0x00000008;
WDT->IER |= 0x00000001;
NVIC_EnableIRQ(WDT_IRQn);
CLK->PWRCTL |= CLK_PWRCTL_WAKEINT_EN; /* Enable wake up interrupt source */
NVIC_EnableIRQ(PDWU_IRQn); /* Enable IRQ request for PDWU interrupt */
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
printf("Enter Power Down Mode >>>>>>>>>>>\n");
u32PWDU_WakeFlag = 0; /* clear software semaphore */
while(!(UART0->FSR & UART_FSR_TX_EMPTY_F_Msk)) ; /* waits for message send out */
CLK_PowerDown();
/* CPU Reset test */
printf("Waits for 5 times WDT interrupts.....\n");
while (u32WDT_Ticks <= 5);
printf("<<<<<<<<<< Program resumes execution.\n");
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Reset CPU */
SYS_ResetCPU();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable external XTAL 12MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set Flash Access Delay */
FMC->FTCTL |= FMC_FTCTL_FOM_Msk;
/* Set core clock */
CLK_SetCoreClock(72000000);
/* Enable module clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(I2C0_MODULE);
CLK_EnableModuleClock(SPI1_MODULE);
/* Select module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PLL, 0);
/* Enable USB LDO33 */
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD.0, PD.1, PD.6, PD.4 and PD.5 as SPI1_I2SMCLK, UART0 TXD, UART0 RXD, I2C0_SDA and I2C0_SCL function pins */
SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_UART0_RXD |
SYS_GPD_MFPL_PD4MFP_I2C0_SDA | SYS_GPD_MFPL_PD5MFP_I2C0_SCL;
/* Set I2S1 interface: I2S1_LRCLK (PA.4), I2S1_DO (PA.5), I2S1_DI (PA.6), I2S1_BCLK (PA.7) */
SYS->GPA_MFPL = SYS_GPA_MFPL_PA4MFP_SPI1_SS | SYS_GPA_MFPL_PA5MFP_SPI1_MOSI | SYS_GPA_MFPL_PA6MFP_SPI1_MISO | SYS_GPA_MFPL_PA7MFP_SPI1_CLK;
/* Set PC.1 as CLKO pin */
SYS->GPC_MFPL = SYS_GPC_MFPL_PC1MFP_CLKO;
/* Enable CLKO (PC.1) for monitor HCLK. CLKO = HCLK/8 Hz */
CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0);
}
