/**
* @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
* @param u32Hclk is HCLK frequency
* @return None
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN) {
CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HXT,u32Hclk);
} else {
CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk);
}
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));
return SystemCoreClock;
}
/*--------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz HXT */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, 96000000);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_PLL_STB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(3));
/* Select IP clock source */
CLK_SetModuleClock(USBD_MODULE, 0, CLK_USB_CLK_DIVIDER(2));
/* Enable IP clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);
SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);
/* Lock protected registers */
SYS_LockReg();
}
/**
* @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
* @param u32Hclk is HCLK frequency
* @return HCLK frequency
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
if(u32Hclk > FREQ_50MHZ)
u32Hclk = FREQ_50MHZ;
else if(u32Hclk < FREQ_25MHZ)
u32Hclk = FREQ_25MHZ;
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);
else
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
return u32Hclk;
}
/**
* @brief Set HCLK frequency
* @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 50 MHz.
* @return HCLK frequency
* @details This function is used to set HCLK frequency. The frequency unit is Hz.
* It would configure PLL frequency to 50MHz ~ 100MHz,
* set HCLK clock divider as 2 and switch HCLK clock source to PLL.
* The register write-protection function should be disabled before using this function.
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
uint32_t u32HIRCSTB;
/* Read HIRC clock source stable flag */
u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
/* The range of u32Hclk is 25 MHz ~ 50 MHz */
if(u32Hclk > FREQ_50MHZ)
u32Hclk = FREQ_50MHZ;
if(u32Hclk < FREQ_25MHZ)
u32Hclk = FREQ_25MHZ;
/* Switch HCLK clock source to HIRC clock for safe */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk);
/* Configure PLL setting if HXT clock is enabled */
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, (u32Hclk << 1));
/* Configure PLL setting if HXT clock is not enabled */
else
{
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, (u32Hclk << 1));
/* Read HIRC clock source stable flag */
u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
}
/* Select HCLK clock source to PLL,
Select HCLK clock source divider as 2
and update system core clock
*/
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Disable HIRC if HIRC is disabled before setting core clock */
if( u32HIRCSTB == 0 )
CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;
/* Return actually HCLK frequency is PLL frequency divide 2 */
return u32Hclk >> 1;
}
void mbed_sdk_init(void)
{
// NOTE: Support singleton semantics to be called from other init functions
static int inited = 0;
if (inited) {
return;
}
inited = 1;
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable HIRC clock (internal OSC 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk);
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
/* Enable LIRC clock (OSC 10KHz) for lp_ticker */
CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk);
/* Enable LXT clock (XTAL 32KHz) for RTC */
CLK_EnableXtalRC(CLK_PWRCTL_LXT_EN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk);
/* Wait for LXT clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk);
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1));
/* Select HXT/HIRC to clock PLL
*
* Comparison between HXT/HIRC-clocked PLL:
* 1. Spare HXT on board if only HIRC is used.
* 2. HIRC has shorter stable time.
* 3. HXT has better accuracy. USBD requires HXT-clocked PLL.
* 4. HIRC has shorter wake-up time from power-down mode.
* Per test, wake-up time from power-down mode would take:
* T1. 1~13 ms (proportional to deep sleep time) with HXT-clocked PLL as HCLK clock source
* T2. <1 ms with HIRC-clocked PLL as HCLK clock source
* T1 will fail Greentea test which requires max 10 ms wake-up time.
*
* If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
* it will go T1 with HXT already enabled in front. So we manually configure
* it to choose HXT/HIRC-clocked PLL.
*/
#define NU_HXT_PLL 1
#define NU_HIRC_PLL 2
#ifndef NU_CLOCK_PLL
#define NU_CLOCK_PLL NU_HIRC_PLL
#endif
#if (NU_CLOCK_PLL == NU_HXT_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#elif (NU_CLOCK_PLL == NU_HIRC_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#endif
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}
int32_t main (void)
{
int tdelay=1000000;
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will Output module clock from PC.0 pin.
*/
printf("+-----------------------------------------+\n");
printf("| Nano100 Module Clock Output Sample Code |\n");
printf("+-----------------------------------------+\n");
/* Enable PLL clock and set PLL clock to 48Mhz */
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC,48000000);
CLK->MCLKO |= CLK_MCLKO_MCLK_EN_Msk ;
printf("This sample code will Output module clock from PC.0 pin.\n");
while(1)
{
printf("MCLK output = ISP_CLK\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_ISP_CLK;
CLK_SysTickDelay(tdelay);
printf("MCLK output = HIRC\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_HIRC;
CLK_SysTickDelay(tdelay);
printf("MCLK output = HXT\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_HXT;
CLK_SysTickDelay(tdelay);
printf("MCLK output = LXT\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_LXT;
CLK_SysTickDelay(tdelay);
printf("MCLK output = LIRC\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_LIRC;
CLK_SysTickDelay(tdelay);
printf("MCLK output = PLL ouptut\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_PLLO;
CLK_SysTickDelay(tdelay);
printf("MCLK output = PLL input\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_PLLI;
CLK_SysTickDelay(tdelay);
printf("MCLK output = sytem tick \n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_SYSTICK;
CLK_SysTickDelay(tdelay);
printf("MCLK output = HCLK\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_ISP_CLK;
CLK_SysTickDelay(tdelay);
printf("MCLK output = PCLK\n");
CLK->MCLKO = (CLK->MCLKO & ~CLK_MCLKO_MCLK_SEL_Msk) | CLK_MCLKO_MCLK_SEL_PCLK;
CLK_SysTickDelay(tdelay);
}
}