void setupSystemClock()
{
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable external XTAL 12MHz clock */
//CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for external XTAL clock ready */
//CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(SYSTEM_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
SYS_LockReg();
}
void setup_system_tick(uint32_t sampleRate)
{
uint32_t tickPeriod = SystemCoreClock/sampleRate;
/* SysTick source to HCLK/2 */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HIRC_DIV2);
SysTick_Config(tickPeriod);
//ChronographStart(ChronMain);
// printf("SystemCoreClock:%d\n",SystemCoreClock);
// printf("Tick Time: %d us\n",1000000/sampleRate);
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P5 multi-function pins for XTAL1 and XTAL2 */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XTAL1 | SYS_MFP_P51_XTAL2);
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_HXT|CLK_PWRCON_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_XTAL,CLK_CLKDIV_HCLK(1));
/* STCLK to XTL STCLK to XTL */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_XTAL);
/* Enable IP clock */
CLK_EnableModuleClock(UART_MODULE);
CLK_EnableModuleClock(I2C_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART_MODULE,CLK_CLKSEL1_UART_S_XTAL,CLK_CLKDIV_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);
SYS->P0_MFP |= (SYS_MFP_P01_RXD | SYS_MFP_P00_TXD);
/* Lock protected registers */
SYS_LockReg();
/* Update System Core Clock */
SystemCoreClockUpdate();
}
void setupSystemClock()
{
#ifdef M451
SYS_UnlockReg();
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(SYSTEM_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
SYS_LockReg();
#else
uint32_t u32PllCr;
uint16_t i;
UNLOCKREG();
DrvSYS_SetOscCtrl(E_SYS_OSC22M, 1);
while (DrvSYS_GetChipClockSourceStatus(E_SYS_OSC22M) != 1);
DrvSYS_SelectPLLSource(E_SYS_INTERNAL_22M);
u32PllCr = DrvSYS_GetPLLContent(E_SYS_INTERNAL_22M, SYSTEM_CLOCK);
/*Delay for 12M or 22M stable*/
for (i=0;i<10000;i++);
DrvSYS_SetPLLContent(u32PllCr);
SYSCLK->PLLCON.OE = 0;
SYSCLK->PLLCON.PD = 0;
/*Delay for PLL stable*/
for (i=0;i<10000;i++);
/* Change HCLK clock source to be PLL. */
DrvSYS_SelectHCLKSource(2);
LOCKREG(); // Lock the protected registers
#endif
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCON_IRC22M_EN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable HXT and LIRC */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_IRC10K_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_IRC10K_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(PLL_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2);
/* Enable peripheral clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(WDT_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_PLL, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, 0);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD, TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M | CLK_PWRCON_OSC10K_EN_Msk | CLK_PWRCON_IRC22M_EN_Msk;
CLK_SysTickDelay(1200);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk);
/* IP clock divider */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_XTAL);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_XTAL,CLK_CLKDIV_HCLK(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART_MODULE);
CLK_EnableModuleClock(TMR1_MODULE);
/* IP clock source */
CLK->CLKSEL1 = ( CLK->CLKSEL1 & (~CLK_CLKSEL1_UART_S_Msk) ) | CLK_CLKSEL1_UART_S_XTAL | CLK_CLKSEL1_TMR1_S_HCLK;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);
SYS->P0_MFP |= (SYS_MFP_P01_RXD | SYS_MFP_P00_TXD);
/* To update the variable SystemCoreClock */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set P5 multi-function pins for XTAL1 and XTAL2 */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);
/* Enable external 12MHz XTAL (UART), and HIRC */
CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_XTLSTB_Msk);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL, CLK_CLKDIV_HCLK(1));
/* STCLK to XTL STCLK to XTL */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_XTAL);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P1 multi-function pins for UART RXD, TXD */
SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD;
/* To update the variable SystemCoreClock */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT and LIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_LIRCEN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk | CLK_STATUS_LIRCSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(PLL_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
/* Enable peripheral clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(WDT_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_PLL, CLK_CLKDIV0_UART(1));
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD, TXD */
SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD;
}
static void rt_hw_system_init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
SYS_UnlockReg();
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(BOARD_PLL_CLOCK);
/* Set SysTick clock source to HCLK source divide 2 */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2);
SYS_LockReg();
}