void PINT_Deinit(PINT_Type *base) { uint32_t i; assert(base); /* Cleanup */ PINT_DisableCallback(base); for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { s_pintCallback[i] = NULL; } #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) /* Reset the peripheral */ RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); /* Disable the peripheral clock */ CLOCK_DisableClock(kCLOCK_GpioInt); #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) /* Reset the peripheral */ RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); /* Disable the peripheral clock */ CLOCK_DisableClock(kCLOCK_Gpio0); #else /* Reset the peripheral */ RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); /* Disable the peripheral clock */ CLOCK_DisableClock(kCLOCK_Pint); #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ }
SECTION("itcm") int rt_hw_flexspi_init(void) { flexspi_config_t config; status_t status; rt_uint32_t level; level = rt_hw_interrupt_disable(); // Set flexspi root clock to 166MHZ. const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26); /* Set PLL3 PFD0 clock 332MHZ. */ CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */ /*Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); /*Set AHB buffer size for reading data through AHB bus. */ config.ahbConfig.enableAHBPrefetch = true; /*Allow AHB read start address do not follow the alignment requirement. */ config.ahbConfig.enableReadAddressOpt = true; /* enable diff clock and DQS */ config.enableSckBDiffOpt = true; config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad; config.enableCombination = true; FLEXSPI_Init(FLEXSPI, &config); /* Configure flash settings according to serial flash feature. */ FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); /* Update LUT table. */ FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); /* Do software reset. */ FLEXSPI_SoftwareReset(FLEXSPI); status = flexspi_nor_hyperflash_cfi(FLEXSPI); /* Get vendor ID. */ if (status != kStatus_Success) { FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return status; } FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return 0; }
SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) { status_t status; flexspi_transfer_t flashXfer; rt_uint32_t level; level = rt_hw_interrupt_disable(); FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); /* Write enable */ status = flexspi_nor_write_enable(base, address); if (status != kStatus_Success) { FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return status; } flashXfer.deviceAddress = address; flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Command; flashXfer.SeqNumber = 4; flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR; status = FLEXSPI_TransferBlocking(base, &flashXfer); if (status != kStatus_Success) { FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return status; } status = flexspi_nor_wait_bus_busy(base); rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE); rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE); FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return status; }
void INPUTMUX_Deinit(INPUTMUX_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE CLOCK_DisableClock(kCLOCK_Sct); CLOCK_DisableClock(kCLOCK_Dma); #else CLOCK_DisableClock(kCLOCK_InputMux); #endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void ELCDIF_Deinit(LCDIF_Type *base) { ELCDIF_Reset(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = ELCDIF_GetInstance(base); /* Disable the clock. */ #if defined(LCDIF_PERIPH_CLOCKS) CLOCK_DisableClock(s_elcdifPixClocks[instance]); #endif CLOCK_DisableClock(s_elcdifApbClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src) { status_t status; flexspi_transfer_t flashXfer; rt_uint32_t level; level = rt_hw_interrupt_disable(); FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); /* Write neable */ status = flexspi_nor_write_enable(base, address); if (status != kStatus_Success) { rt_hw_interrupt_enable(level); return status; } /* Prepare page program command */ flashXfer.deviceAddress = address; flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Write; flashXfer.SeqNumber = 2; flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; flashXfer.data = (uint32_t *)src; flashXfer.dataSize = FLASH_PAGE_SIZE; status = FLEXSPI_TransferBlocking(base, &flashXfer); if (status != kStatus_Success) { rt_hw_interrupt_enable(level); return status; } status = flexspi_nor_wait_bus_busy(base); rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE); rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE); FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); rt_hw_interrupt_enable(level); return status; }
bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) { bool ret = true; CLOCK_DisableClock(kCLOCK_Usbfs0); if (kCLOCK_UsbSrcExt == src) { SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; } else { SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK; } CLOCK_EnableClock(kCLOCK_Usbfs0); if (kCLOCK_UsbSrcIrc48M == src) { USB0->CLK_RECOVER_IRC_EN = 0x03U; USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; } return ret; }
void TSI_Deinit(TSI_Type *base) { base->GENCS = 0U; base->DATA = 0U; base->TSHD = 0U; CLOCK_DisableClock(kCLOCK_Tsi0); }
/*! * brief De-initialize the PXP. * * This function disables the PXP peripheral clock. * * param base PXP peripheral base address. */ void PXP_Deinit(PXP_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = PXP_GetInstance(base); CLOCK_DisableClock(s_pxpClocks[instance]); #endif }
void LPTMR_Deinit(LPTMR_Type *base) { /* Disable the LPTMR and reset the internal logic */ base->CSR &= ~LPTMR_CSR_TEN_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = LPTMR_GetInstance(base); /* Gate the LPTMR clock*/ CLOCK_DisableClock(s_lptmrClocks[instance]); #if defined(LPTMR_PERIPH_CLOCKS) CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void SPIFI_Deinit(SPIFI_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the SAI clock */ CLOCK_DisableClock(s_spifiClock[SPIFI_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) { /* RTC clock gate enable */ CLOCK_EnableClock(kCLOCK_Rtc0); if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ /* Set the specified capacitor configuration for the RTC oscillator */ RTC_SetOscCapLoad(RTC, capLoad); /* Enable the RTC 32KHz oscillator */ RTC->CR |= RTC_CR_OSCE_MASK; } /* Output to other peripherals */ if (enableOutPeriph) { RTC->CR &= ~RTC_CR_CLKO_MASK; } else { RTC->CR |= RTC_CR_CLKO_MASK; } /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); /* Set RTC_TSR if there is fault value in RTC */ if (RTC->SR & RTC_SR_TIF_MASK) { RTC -> TSR = RTC -> TSR; } /* RTC clock gate disable */ CLOCK_DisableClock(kCLOCK_Rtc0); }
void RNGA_Deinit(RNG_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the clock for RNGA module.*/ CLOCK_DisableClock(kCLOCK_Rnga0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void DAC_Deinit(DAC_Type *base) { DAC_Enable(base, false); /* Disable the clock. */ CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); }
/*! * brief Disables the module and gates the LPIT clock. * * param base LPIT peripheral base address. */ void LPIT_Deinit(LPIT_Type *base) { /* Disable the module */ base->MCR &= ~LPIT_MCR_M_CEN_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = LPIT_GetInstance(base); /* Disable the clock */ CLOCK_DisableClock(s_lpitClock[instance]); #if defined(LPIT_PERIPH_CLOCKS) CLOCK_DisableClock(s_lpitPeriphClocks[instance]); #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void PDB_Deinit(PDB_Type *base) { PDB_Enable(base, false); /* Disable the PDB module. */ /* Disable the clock. */ CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]); }
void UTICK_Deinit(UTICK_Type *base) { /* Turn off utick */ base->CTRL = 0; /* Disable utick clock */ CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); }
void LPTMR_Deinit(LPTMR_Type *base) { /* Disable the LPTMR and reset the internal logic */ base->CSR &= ~LPTMR_CSR_TEN_MASK; /* Gate the LPTMR clock*/ CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]); }
void TPM_Deinit(TPM_Type *base) { /* Stop the counter */ base->SC &= ~TPM_SC_CMOD_MASK; /* Gate the TPM clock */ CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]); }
void FTM_Deinit(FTM_Type *base) { /* Set clock source to none to disable counter */ base->SC &= ~(FTM_SC_CLKS_MASK); /* Gate the FTM clock */ CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]); }
void CMP_Deinit(CMP_Type *base) { /* Disable the CMP module. */ CMP_Enable(base, false); /* Disable the clock. */ CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); }
void CSI_Deinit(CSI_Type *base) { /* Disable transfer first. */ CSI_Stop(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance = CSI_GetInstance(base); CLOCK_DisableClock(s_csiClocks[instance]); #endif }
static void CLOCK_CONFIG_EnableIrc48MOsc() { /* USB clock gate enable */ CLOCK_EnableClock(kCLOCK_Usbfs0); /* IRC48M oscillator enable */ USB0->CLK_RECOVER_IRC_EN = USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK | USB_CLK_RECOVER_IRC_EN_REG_EN_MASK; /* USB clock gate disable */ CLOCK_DisableClock(kCLOCK_Usbfs0); }
void TSI_Deinit(TSI_Type *base) { base->GENCS = 0U; base->DATA = 0U; base->TSHD = 0U; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Tsi0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
static void SetFlexSPIDiv(uint32_t div) { FLEXSPI_Enable(FLEXSPI, false); CLOCK_DisableClock(FLEXSPI_CLOCK); CLOCK_SetDiv(kCLOCK_FlexspiDiv, div); /* flexspi clock 332M, DDR mode, internal clock 166M. */ CLOCK_EnableClock(FLEXSPI_CLOCK); FLEXSPI_Enable(FLEXSPI, true); FLEXSPI_SoftwareReset(FLEXSPI); // not sure why this is needed, but SDK example does it. }
void PIT_Deinit(PIT_Type *base) { /* Disable PIT timers */ base->MCR |= PIT_MCR_MDIS_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Gate the PIT clock*/ CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void GPT_Deinit(GPT_Type *base) { /* Disable GPT timers */ base->CR = 0U; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Gate the GPT clock*/ CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
/*! * brief Stops the counter and gates the Quad Timer clock * * param base Quad Timer peripheral base address * param channel Quad Timer channel number */ void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) { /* Stop the counter */ base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the module clock */ CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }
void EWM_Deinit(EWM_Type *base) { EWM_DisableInterrupts(base, kEWM_InterruptEnable); #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Ewm0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ }
void CMP_Deinit(CMP_Type *base) { /* Disable the CMP module. */ CMP_Enable(base, false); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the clock. */ CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ }