SECTION("itcm") int rt_hw_flexspi_init(void)
{
flexspi_config_t config;
status_t status;
rt_uint32_t level;
level = rt_hw_interrupt_disable();
// Set flexspi root clock to 166MHZ.
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26); /* Set PLL3 PFD0 clock 332MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */
/*Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);
/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
/*Allow AHB read start address do not follow the alignment requirement. */
config.ahbConfig.enableReadAddressOpt = true;
/* enable diff clock and DQS */
config.enableSckBDiffOpt = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
config.enableCombination = true;
FLEXSPI_Init(FLEXSPI, &config);
/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
/* Update LUT table. */
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
/* Do software reset. */
FLEXSPI_SoftwareReset(FLEXSPI);
status = flexspi_nor_hyperflash_cfi(FLEXSPI);
/* Get vendor ID. */
if (status != kStatus_Success)
{
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return status;
}
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return 0;
}
SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
{
status_t status;
flexspi_transfer_t flashXfer;
rt_uint32_t level;
level = rt_hw_interrupt_disable();
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
/* Write enable */
status = flexspi_nor_write_enable(base, address);
if (status != kStatus_Success)
{
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return status;
}
flashXfer.deviceAddress = address;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Command;
flashXfer.SeqNumber = 4;
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
status = FLEXSPI_TransferBlocking(base, &flashXfer);
if (status != kStatus_Success)
{
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return status;
}
status = flexspi_nor_wait_bus_busy(base);
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return status;
}
SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
{
status_t status;
flexspi_transfer_t flashXfer;
rt_uint32_t level;
level = rt_hw_interrupt_disable();
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
/* Write neable */
status = flexspi_nor_write_enable(base, address);
if (status != kStatus_Success)
{
rt_hw_interrupt_enable(level);
return status;
}
/* Prepare page program command */
flashXfer.deviceAddress = address;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Write;
flashXfer.SeqNumber = 2;
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
flashXfer.data = (uint32_t *)src;
flashXfer.dataSize = FLASH_PAGE_SIZE;
status = FLEXSPI_TransferBlocking(base, &flashXfer);
if (status != kStatus_Success)
{
rt_hw_interrupt_enable(level);
return status;
}
status = flexspi_nor_wait_bus_busy(base);
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI);
rt_hw_interrupt_enable(level);
return status;
}
void us_ticker_setup_clock()
{
/* Set PERCLK_CLK source to OSC_CLK*/
CLOCK_SetMux(kCLOCK_PerclkMux, 1U);
/* Set PERCLK_CLK divider to 1 */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 0U);
}
static void SetFlexSPIDiv(uint32_t div)
{
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, div); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
FLEXSPI_SoftwareReset(FLEXSPI); // not sure why this is needed, but SDK example does it.
}
static void rt1052_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
{
GPT_Type *hwtimer_dev;
gpt_config_t gptConfig;
hwtimer_dev = (GPT_Type *)timer->parent.user_data;
RT_ASSERT(timer != RT_NULL);
GPT_Deinit(hwtimer_dev);
if (state == 1)
{
/*Clock setting for GPT*/
CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
/* Initialize GPT module by default config */
GPT_GetDefaultConfig(&gptConfig);
GPT_Init(hwtimer_dev, &gptConfig);
}
}
int imxrt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
/* Configure UART divider to default */
CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &imxrt_uart_ops;
uarts[i].serial->config = config;
/* register UART device */
rt_hw_serial_register(uarts[i].serial,
uarts[i].device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
(void *)&uarts[i]);
}
return 0;
}
static rt_err_t icodec_init(struct rt_audio_device *audio)
{
sai_config_t config;
uint32_t mclkSourceClockHz = 0U;
edma_config_t dmaConfig = {0};
lpi2c_master_config_t i2cConfig = {0};
uint32_t i2cSourceClock;
clock_audio_pll_config_t audioPllConfig = {32, 1, 77, 100};
struct imxcodec *icodec = audio->parent.user_data;
sai_transfer_format_t *format;
icodec->sai = DEMO_SAI;
format = &icodec->format;
_InitPins();
CLOCK_InitAudioPll(&audioPllConfig);
/*Clock setting for LPI2C*/
CLOCK_SetMux(kCLOCK_Lpi2cMux, DEMO_LPI2C_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, DEMO_LPI2C_CLOCK_SOURCE_DIVIDER);
/*Clock setting for SAI1*/
CLOCK_SetMux(kCLOCK_Sai1Mux, DEMO_SAI1_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER);
CLOCK_SetDiv(kCLOCK_Sai1Div, DEMO_SAI1_CLOCK_SOURCE_DIVIDER);
/*Enable MCLK clock*/
BOARD_EnableSaiMclkOutput(true);
/* Create EDMA handle */
EDMA_GetDefaultConfig(&dmaConfig);
EDMA_Init(EXAMPLE_DMA, &dmaConfig);
EDMA_CreateHandle(&icodec->dmaHandle, EXAMPLE_DMA, EXAMPLE_CHANNEL);
DMAMUX_Init(DMAMUX0);
DMAMUX_SetSource(DMAMUX0, EXAMPLE_CHANNEL, EXAMPLE_SAI_TX_SOURCE);
DMAMUX_EnableChannel(DMAMUX0, EXAMPLE_CHANNEL);
/* Init SAI module */
SAI_TxGetDefaultConfig(&config);
config.protocol = kSAI_BusLeftJustified;
SAI_TxInit(DEMO_SAI, &config);
/* Configure the audio format */
format->bitWidth = kSAI_WordWidth16bits;
format->channel = 0U;
format->sampleRate_Hz = kSAI_SampleRate48KHz;
format->masterClockHz = DEMO_SAI_CLK_FREQ;
format->protocol = config.protocol;
format->stereo = kSAI_Stereo;
format->isFrameSyncCompact = 0;
format->watermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U;
/* Configure Sgtl5000 I2C */
icodec->codecHandle.base = DEMO_I2C;
icodec->codecHandle.i2cHandle = &icodec->i2cHandle;
i2cSourceClock = DEMO_I2C_CLK_FREQ;
LPI2C_MasterGetDefaultConfig(&i2cConfig);
LPI2C_MasterInit(DEMO_I2C, &i2cConfig, i2cSourceClock);
LPI2C_MasterTransferCreateHandle(DEMO_I2C, &icodec->i2cHandle, NULL, NULL);
WM8960_Init(&icodec->codecHandle, NULL);
WM8960_ConfigDataFormat(&icodec->codecHandle, format->masterClockHz, format->sampleRate_Hz, format->bitWidth);
SAI_TransferTxCreateHandleEDMA(icodec->sai, &icodec->txHandle, saidma_callback, audio, &icodec->dmaHandle);
mclkSourceClockHz = DEMO_SAI_CLK_FREQ;
SAI_TransferTxSetFormatEDMA(icodec->sai, &icodec->txHandle, format, mclkSourceClockHz, format->masterClockHz);
return RT_EOK;
}
int flexspi_nor_init(void)
{
uint32_t i = 0;
flexspi_config_t config;
status_t status;
#ifdef XIP_EXTERNAL_FLASH
return 0;
#endif
// Set flexspi root clock to 166MHZ.
// NOTE! we assuem PLL3 (USBPLL1) has been locked to 480MHz already
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26); /* Set PLL3 PFD0 clock 332MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */
SCB_DisableDCache();
PRINTF("FLEXSPI hyperflash example started!\r\n");
/*Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);
/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
/* enable diff clock and DQS */
config.enableSckBDiffOpt = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
config.enableCombination = true;
FLEXSPI_Init(FLEXSPI, &config);
/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
/* Update LUT table. */
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
/* Do software reset. */
FLEXSPI_SoftwareReset(FLEXSPI);
status = flexspi_nor_hyperflash_cfi(FLEXSPI);
/* Get vendor ID. */
if (status != kStatus_Success)
{
return status;
}
return 0;
/* Erase sectors. */
PRINTF("Erasing Serial NOR over FlexSPI...\r\n");
status = flexspi_nor_flash_erase_sector(FLEXSPI, SECTOR * SECTOR_SIZE);
if (status != kStatus_Success)
{
PRINTF("Erase sector failure !\r\n");
return -1;
}
/* Do software reset. */
FLEXSPI_SoftwareReset(FLEXSPI);
memset(s_hyperflash_program_buffer, 0xFF, sizeof(s_hyperflash_program_buffer));
memcpy(s_hyperflash_read_buffer, (void *)(FlexSPI_AMBA_BASE + SECTOR * SECTOR_SIZE),
sizeof(s_hyperflash_read_buffer));
if (memcmp(s_hyperflash_program_buffer, s_hyperflash_read_buffer, sizeof(s_hyperflash_program_buffer)))
{
PRINTF("Erase data - read out data value incorrect !\r\n ");
return -1;
}
else
{
PRINTF("Erase data - successfully. \r\n");
}
for (i = 0; i < sizeof(s_hyperflash_program_buffer); i++)
{
s_hyperflash_program_buffer[i] = i & 0xFFU;
}
status = flexspi_nor_flash_page_program(FLEXSPI, SECTOR * SECTOR_SIZE,
(void *)s_hyperflash_program_buffer);
if (status != kStatus_Success)
{
PRINTF("Page program failure !\r\n");
return -1;
}
/* Program finished, speed the clock to 166M. */
FLEXSPI_Enable(FLEXSPI, false);
CLOCK_DisableClock(FLEXSPI_CLOCK);
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
CLOCK_EnableClock(FLEXSPI_CLOCK);
FLEXSPI_Enable(FLEXSPI, true);
/* Do software reset to reset AHB buffer. */
FLEXSPI_SoftwareReset(FLEXSPI);
memcpy(s_hyperflash_read_buffer, (void *)(FlexSPI_AMBA_BASE + SECTOR * SECTOR_SIZE),
sizeof(s_hyperflash_read_buffer));
if (memcmp(s_hyperflash_read_buffer, s_hyperflash_program_buffer, sizeof(s_hyperflash_program_buffer)) != 0)
{
PRINTF("Program data - read out data value incorrect !\r\n ");
return -1;
}
else
{
PRINTF("Program data - successfully. \r\n");
}
while (1)
{
}
}
void i2c_setup_clock()
{
/* Select USB1 PLL (480 MHz) as master lpi2c clock source */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0U);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER);
}
void spi_setup_clock()
{
/*Set clock source for LPSPI*/
CLOCK_SetMux(kCLOCK_LpspiMux, 1U);
CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLOCK_SOURCE_DIVIDER);
}
