void shiftReg_initialise() {
SIM->SCGC5 |= PORT_CLOCK_MASK( SHIFTREG_CLK_PORT );
CLR_PIN( SHIFTREG_CLK_PORT, SHIFTREG_CLK_PIN );
PDDR( SHIFTREG_CLK_PORT ) |= ( 1 << SHIFTREG_CLK_PIN );
PCR( SHIFTREG_CLK_PORT, SHIFTREG_CLK_PIN ) = PORT_PCR_MUX(1)|PORT_PCR_DSE_MASK;
SIM->SCGC5 |= PORT_CLOCK_MASK( SHIFTREG_SHOW_PORT );
CLR_PIN( SHIFTREG_SHOW_PORT, SHIFTREG_SHOW_PIN );
PDDR( SHIFTREG_SHOW_PORT ) |= ( 1 << SHIFTREG_SHOW_PIN );
PCR( SHIFTREG_SHOW_PORT, SHIFTREG_SHOW_PIN ) = PORT_PCR_MUX(1)|PORT_PCR_DSE_MASK;
SIM->SCGC5 |= PORT_CLOCK_MASK( SHIFTREG_RST_PORT );
SET_PIN( SHIFTREG_RST_PORT, SHIFTREG_RST_PIN );
PDDR( SHIFTREG_RST_PORT ) |= ( 1 << SHIFTREG_RST_PIN );
PCR( SHIFTREG_RST_PORT, SHIFTREG_RST_PIN ) = PORT_PCR_MUX(1)|PORT_PCR_DSE_MASK;
}
int main(int argc, char **argv)
{
int g,rep;
int i=0;
int repCount = 10;
double dutyCycle = 0.50;
time_t waitTime = 1000000*30; // Default 30ms per blink
// Wait time in ms
if (argc > 1) waitTime=atoi( argv[1] )*1000;
// number of reps
if (argc > 2) repCount=atoi( argv[2] );
// pulse width duty cycle
if (argc > 3) dutyCycle=(double)(atoi(argv[3])/100.0);
if (dutyCycle > 1.0) dutyCycle = 1.0;
if (dutyCycle < 0.0) dutyCycle = 0.0;
// Set up gpi pointer for direct register access
setup_io();
struct timespec waitStruct;
waitStruct.tv_sec = 0;
waitStruct.tv_nsec = (time_t)(waitTime*dutyCycle);
struct timespec waitStructLo;
waitStructLo.tv_sec = 0;
waitStructLo.tv_nsec = (time_t)(waitTime*(1.0-dutyCycle));
for (i=0;i<nPins;i++)
{
//INP_GPIO( pins[i] ); // must use INP_GPIO before we can use OUT_GPIO
//OUT_GPIO( pins[i] );
init_output( pins[i] );
}
for (rep=0; rep<repCount; rep++)
{
for (i = 0; i < nPins; i++)
{
SET_PIN( pins[i] );
}
nanosleep(&waitStruct, NULL);
for (i = 0; i < nPins; i++)
{
CLR_PIN( pins[i] );
}
nanosleep(&waitStructLo,NULL);
}
GPIO_CLR = 1<<pins[0] | 1<<pins[1] | 1<<pins[2];
return 0;
} // main
void shiftRegWrite( unsigned int shiftValue ) {
// Ensure we're only dealing with values from 0 to 8
if( shiftValue > 8 ) {
shiftValue = 8;
}
// Reset shift register
CLR_PIN( SHIFTREG_RST_PORT, SHIFTREG_RST_PIN );
SET_PIN( SHIFTREG_RST_PORT, SHIFTREG_RST_PIN );
while( shiftValue > 0 ) {
CLR_PIN( SHIFTREG_CLK_PORT, SHIFTREG_CLK_PIN );
SET_PIN( SHIFTREG_CLK_PORT, SHIFTREG_CLK_PIN );
shiftValue--;
}
// Enable write to shift register
SET_PIN( SHIFTREG_SHOW_PORT, SHIFTREG_SHOW_PIN );
CLR_PIN( SHIFTREG_SHOW_PORT, SHIFTREG_SHOW_PIN );
}
__noreturn int main()
{
s16 result;
u32 ul;
__disable_interrupt();
//*** Hardware Init ***
/* When using the JTAG debugger the hardware is not always initialised to
the correct default state. This line just ensures that this does not
cause all interrupts to be masked at the start. */
AT91C_BASE_AIC->AIC_EOICR = 0;
/* Enable the peripheral clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;
// This Pull ups are disabled
*AT91C_PIOB_PPUDR = (AT91C_PIO_PB5|AT91C_PIO_PB6|AT91C_PIO_PB13|AT91C_PIO_PB14|AT91C_PIO_PB26);
AT91F_PIO_CfgPeriph(PIOA, 0, 0);
AT91F_PIO_CfgPeriph(PIOB, 0, 0);
CLR_PIN(PIOB, AT91C_PB18_EF100);
SET_OUTPUT(PIOA, AT91C_PA22_TK|AT91C_PA21_TF|AT91C_PA0_RXD0);
SET_OUTPUT(PIOB, AT91C_PIO_PB21);
// Release Reset of the CODEC
NET_init(RX_buf, TX_buf);
EMAC_Init();
__enable_interrupt();
u8 buf[10];
buf[0] = 0x03;
buf[1] = 0x4B;
I2C_Init(100);
CODEC_init();
RING_init(_CODEC_DATA_START_ADR, _CODEC_DATABLOCK_SIZE, _CODEC_NUM_OF_BUFS);
// Init the UWSDR sub system
UWSDR_init();
//CODEC_start();
//*********** THE MAIN LOOP ************
_DBG_STATE_POS(_DBG_STATE_MAIN);
while(1) {
result = EMAC_Poll();
_DBG_STATE_POS(_DBG_STATE_MAIN);
if(result == _NET_GOT_RX_DATA) {
NET_process();
}
_DBG_STATE_POS(_DBG_STATE_MAIN);
ul = AT91C_BASE_SSC->SSC_SR;
if((ul & AT91C_SSC_ENDRX) && CODEC_IS_MODE(CODEC_MODE_RX)) {
// DBG_LED1_ON();
CODEC_SSC_ISR();
UWSDR_upload();
// DBG_LED1_OFF();
}
if(ul & AT91C_SSC_ENDRX && CODEC_IS_MODE(CODEC_MODE_TX)) {
CODEC_SSC_ISR();
}
_DBG_STATE_POS(_DBG_STATE_MAIN);
}
}
