コード例 #1
0
    RK1108_CLKGATE_CON(7), 2, GFLAGS),
    COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
    RK1108_CLKSEL_CON(29), 8, 5, DFLAGS,
    RK1108_CLKGATE_CON(7), 3, GFLAGS),

    INVERTER(0, "pclk_vip", "ext_vip",
    RK1108_CLKSEL_CON(31), 8, IFLAGS),
    GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
    RK1108_CLKGATE_CON(7), 6, GFLAGS),
    GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
    RK1108_CLKGATE_CON(18), 10, GFLAGS),
    GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
    RK1108_CLKGATE_CON(6), 5, GFLAGS),
    GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
    RK1108_CLKGATE_CON(6), 4, GFLAGS),
    COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
    RK1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),

    /*
     * Clock-Architecture Diagram 5
     */

    FACTOR(0, "xin12m", "xin24m", 0, 1, 2),

    COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
    RK1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
    RK1108_CLKGATE_CON(2), 0, GFLAGS),
    COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
    RK1108_CLKSEL_CON(8), 0,
    RK1108_CLKGATE_CON(2), 1, GFLAGS,
    &rk1108_i2s0_fracmux),
    GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
コード例 #2
0
ファイル: clk-rk3288.c プロジェクト: Seagate/SMR_FS-EXT4
	COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
			RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
			RK3288_CLKGATE_CON(12), 8, GFLAGS),
	GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
			RK3288_CLKGATE_CON(12), 9, GFLAGS),
	GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(12), 10, GFLAGS),
	GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
			RK3288_CLKGATE_CON(12), 11, GFLAGS),

	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(0), 8, GFLAGS),
	GATE(0, "gpll_ddr", "gpll", 0,
			RK3288_CLKGATE_CON(0), 9, GFLAGS),
	COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
			RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
					DFLAGS | CLK_DIVIDER_POWER_OF_TWO),

	GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(0), 10, GFLAGS),
	GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(0), 11, GFLAGS),
	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
			RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
	DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
			RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(0), 3, GFLAGS),
	COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
			RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
			RK3288_CLKGATE_CON(0), 5, GFLAGS),
コード例 #3
0
ファイル: clk-rk3368.c プロジェクト: AlexShiLucky/linux
			RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),

	DIV(0, "aclkm_core_l", "armclkl", 0,
			RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
	DIV(0, "atclk_core_l", "armclkl", 0,
			RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
	DIV(0, "pclk_dbg_l", "armclkl", 0,
			RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),

	GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
			RK3368_CLKGATE_CON(0), 9, GFLAGS),
	GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
			RK3368_CLKGATE_CON(0), 10, GFLAGS),
	GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
			RK3368_CLKGATE_CON(0), 8, GFLAGS),
	COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
			RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
	COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
			RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
			RK3368_CLKGATE_CON(0), 13, GFLAGS),

	COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
			RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
			RK3368_CLKGATE_CON(0), 12, GFLAGS),
	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),

	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
			RK3368_CLKGATE_CON(1), 8, GFLAGS),
	GATE(0, "gpll_ddr", "gpll", 0,
			RK3368_CLKGATE_CON(1), 9, GFLAGS),
	COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
			RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
コード例 #4
0
	{ .val = 2, .div = 3 },
	{ .val = 3, .div = 4 },
	{ .val = 4, .div = 8 },
	{ /* sentinel */ },
};

PNAME(mux_hsicphy_p)		= { "sclk_otgphy0", "sclk_otgphy1",
				    "gpll", "cpll" };

static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
	COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
			RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
			div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),

	/* do not source aclk_cpu_pre from the apll, to keep complexity down */
	COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
			RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
	DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
	DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
	COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
			RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
			RK2928_CLKGATE_CON(4), 9, GFLAGS),

	GATE(CORE_L2C, "core_l2c", "armclk", 0,
			RK2928_CLKGATE_CON(9), 4, GFLAGS),

	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
			RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
			RK2928_CLKGATE_CON(2), 0, GFLAGS),
コード例 #5
0
ファイル: clk-rk3328.c プロジェクト: CCNITSilchar/linux
	COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
			RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
			RK3328_CLKGATE_CON(5), 0, GFLAGS),
	COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
			RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
			RK3328_CLKGATE_CON(5), 1, GFLAGS),
	COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
			RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
			RK3328_CLKGATE_CON(5), 5, GFLAGS),
	GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
			RK3328_CLKGATE_CON(5), 4, GFLAGS),

	COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
			RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
			RK3328_CLKGATE_CON(5), 3, GFLAGS),
	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
			RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),

	COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
			RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
			RK3328_CLKGATE_CON(5), 6, GFLAGS),
	DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
			RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
	MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
			RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),

	/*
	 * Clock-Architecture Diagram 7
	 */

	/* PD_PERI */
	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
コード例 #6
0
	/* PD_MISC */
	MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
			RK2928_MISC_CON, 13, 1, MFLAGS),
	MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
			RK2928_MISC_CON, 14, 1, MFLAGS),
	MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
			RK2928_MISC_CON, 15, 1, MFLAGS),

	/* PD_BUS */
	GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 1, GFLAGS),
	GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 1, GFLAGS),
	GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 1, GFLAGS),
	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
	GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
			RK2928_CLKGATE_CON(6), 0, GFLAGS),
	COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
			RK2928_CLKGATE_CON(6), 1, GFLAGS),
	COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
			RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
			RK2928_CLKGATE_CON(6), 2, GFLAGS),
	GATE(0, "pclk_cpu", "pclk_bus_src", 0,
			RK2928_CLKGATE_CON(6), 3, GFLAGS),
	GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
			RK2928_CLKGATE_CON(6), 4, GFLAGS),
	GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
			RK2928_CLKGATE_CON(6), 13, GFLAGS),
コード例 #7
0
ファイル: clk-rk3036.c プロジェクト: avagin/linux
	 */

	GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 6, GFLAGS),

	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),

	/*
	 * Clock-Architecture Diagram 2
	 */

	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 2, GFLAGS),
	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 8, GFLAGS),
	COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
			RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
	FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),

	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
			RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
			RK2928_CLKGATE_CON(0), 7, GFLAGS),
	COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
			RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
			RK2928_CLKGATE_CON(0), 7, GFLAGS),

	GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
	GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
			RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(0), 3, GFLAGS),
コード例 #8
0
ファイル: clk-rv1108.c プロジェクト: AlexShiLucky/linux
	COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
			RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
			RV1108_CLKGATE_CON(8), 14, GFLAGS),
	GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
			RV1108_CLKGATE_CON(8), 13, GFLAGS),

	/*
	 * Clock-Architecture Diagram 3
	 */
	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
			RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
			RV1108_CLKGATE_CON(9), 8, GFLAGS),
	COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
			RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
			RV1108_CLKGATE_CON(9), 11, GFLAGS),
	COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
			RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
	COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
			RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
			RV1108_CLKGATE_CON(9), 12, GFLAGS),

	GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
			RV1108_CLKGATE_CON(14), 6, GFLAGS),
	GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
			RV1108_CLKGATE_CON(14), 14, GFLAGS),

	GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
			RV1108_CLKGATE_CON(18), 10, GFLAGS),
	GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
			RV1108_CLKGATE_CON(18), 10, GFLAGS),
	COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
			RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,