static void GetGPIOPinName(){ if (GPIO_INSTANCE_PIN_NUMBER >= 0 || GPIO_INSTANCE_PIN_NUMBER <= 7){ GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 8 || GPIO_INSTANCE_PIN_NUMBER <= 11){ switch(GPIO_INSTANCE_PIN_NUMBER){ case 8: GPIOPinMuxSetup(CONTROL_CONF_UART_RTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 9: GPIOPinMuxSetup(CONTROL_CONF_UART_CTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 10: GPIOPinMuxSetup(CONTROL_CONF_UART_RXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 11: GPIOPinMuxSetup(CONTROL_CONF_UART_TXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; } }else if (GPIO_INSTANCE_PIN_NUMBER >= 12 || GPIO_INSTANCE_PIN_NUMBER <= 14){ GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 16 || GPIO_INSTANCE_PIN_NUMBER <= 27){ int PIN_REFERENCE = GPIO_INSTANCE_PIN_NUMBER - 16; GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(PIN_REFERENCE), CONTROL_CONF_MUXMODE(PIN_REFERENCE)); }else if (GPIO_INSTANCE_PIN_NUMBER == 28) { GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N , CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 29 || GPIO_INSTANCE_PIN_NUMBER <= 31){ } }
unsigned int GPIO1Pin2PinMuxSetup(void) { unsigned int profile = 7; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { case 0: case 3: //HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) = HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ((CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN | CONTROL_CONF_MUXMODE(7)) & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)); status = TRUE; break; case 1: case 2: case 4: case 5: case 6: case 7: default: break; } return status; }
/** * \brief This function does the Pin Multiplexing and selects GPIO pin * GPIO1[4] for use. GPIO1[4] means 4th pin of GPIO1 instance. * This pin can be used to toggle User Led 4. * * \param None * */ void GPIO1Pin4PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) = (CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE | CONTROL_CONF_MUXMODE(7)); }
void modulo1(int nGpio){ int num; switch(nGpio){ case GPIO_0 ... GPIO_7: GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(nGpio), CONTROL_CONF_MUXMODE(7)); break; case GPIO_12 ... GPIO_15: GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(7), CONTROL_CONF_MUXMODE(7)); break; case GPIO_8 ... GPIO_11: selectUART(nGpio); break; case GPIO_16 ... GPIO_27: num = nGpio - 16; GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_28: GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N, CONTROL_CONF_MUXMODE(7)); break; case GPIO_29 ... GPIO_31: selectCSN(nGpio); break; } }
void HSMMCSDPinMuxSetup(void) { // SD-Card HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT3) = (0 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT2) = (0 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT1) = (0 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT0) = (0 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_CLK) = (0 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_CMD) = (0 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = (5 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE_SHIFT) | (0 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN_SHIFT) | (1 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE_SHIFT); //eMMC //P8 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(0))=CONTROL_CONF_MUXMODE(1); //25 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(1))=CONTROL_CONF_MUXMODE(1); //24 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(2))=CONTROL_CONF_MUXMODE(1); // 5 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(3))=CONTROL_CONF_MUXMODE(1); // 6 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(4))=CONTROL_CONF_MUXMODE(1); //23 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(5))=CONTROL_CONF_MUXMODE(1); //22 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(6))=CONTROL_CONF_MUXMODE(1); // 3 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(7))=CONTROL_CONF_MUXMODE(1); // 4 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_CSN(2))=CONTROL_CONF_MUXMODE(2); //20 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_CSN(1))=CONTROL_CONF_MUXMODE(2); //21 }
/** * \brief This function does the Pin Multiplexing and selects GPIO1[2] * for use. By GPIO1[2], we mean 2nd pin of GPIO1 instance. * * \param None * * \return none */ void GPIO1Pin2PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ((CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN | CONTROL_CONF_MUXMODE(7)) & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)); }
/* ** This function enables GPIO1 pins */ void GPIO1PinMuxSetup(unsigned int pinNo) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(pinNo)) = (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL | /* Slew rate slow */ CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | /* Receiver enabled */ (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN)) | /* PU_PD enabled */ (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)) | /* PD */ (CONTROL_CONF_MUXMODE(7)) /* Select mode 7 */ ); }
// TODO: need to init more pins here void gpioPinMux(void) { // gpio1 pin 23 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = CONTROL_CONF_MUXMODE(7); // HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = CONTROL_CONF_MUXMODE(7); // HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = CONTROL_CONF_MUXMODE(7); }
unsigned int NANDPinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch (profile) { /* All profiles have the same setting. */ case 0: case 1: case 4: case 5: case 6: case 7: /* GPMC_AD0 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) = ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT); /* GPMC_AD1 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) = ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ; /* GPMC_AD2 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ; /* GPMC_AD3 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) = ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ; /* GPMC_AD4 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) = ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ; /* GPMC_AD5 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) = ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ; /* GPMC_AD6 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) = ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ; /* GPMC_AD7 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) = ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ; /* GPMC_AD8 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8)) = ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT) ; /* GPMC_AD9 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9)) = ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT) ; /* GPMC_AD10 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10)) = ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT) ; /* GPMC_AD11 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11)) = ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT) ; /* GPMC_AD12 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12)) = ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT) ; /* GPMC_AD13 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13)) = ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT) ; /* GPMC_AD14 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14)) = ( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT) ; /* GPMC_AD15 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15)) = ( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT) ; /* GPMC_WAIT0 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) = ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)| ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT); /* GPMC_WPN */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) = ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT); /* GPMC_CS0 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) = ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT)| ( 1 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT)| ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT); /* GPMC_ALE */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_ADVN_ALE) = ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT ) | ( 1 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT); /* GPMC_BE0N_CLE */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) = ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT ) | ( 1 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT); /* GPMC_OEN_REN */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT ) | ( 1 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT); /* GPMC_WEN */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) = ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT); status = TRUE; break; case 2: case 3: break; default: break; } return status; }
void modulo0(int nGpio){ int num; switch(nGpio){ case GPIO_0 ... GPIO_1: selectMDIO(nGpio); break; case GPIO_2 ... GPIO_6: selectSPI0(nGpio); break; case GPIO_7: GPIOPinMuxSetup(CONTROL_CONF_ECAP0_IN_PWM0_OUT, CONTROL_CONF_MUXMODE(7)); break; case GPIO_8 ... GPIO_11: num = nGpio + 4; GPIOPinMuxSetup(CONTROL_CONF_LCD_DATA(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_12 ... GPIO_15: selectUART(nGpio); break; case GPIO_16 ... GPIO_17: selectMII(nGpio); break; case GPIO_18: GPIOPinMuxSetup(CONTROL_CONF_USB_DRVVBUS(0), CONTROL_CONF_MUXMODE(7)); break; case GPIO_19 ... GPIO_20: selectXDMA(nGpio); break; case GPIO_21: selectMII(nGpio); break; case GPIO_22 ... GPIO_23: num = nGpio - 14; GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_26 ... GPIO_27: num = nGpio - 16; GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_28: selectMII(nGpio); break; case GPIO_29: GPIOPinMuxSetup(CONTROL_CONF_RMII1_REFCLK, CONTROL_CONF_MUXMODE(7)); break; case GPIO_30: GPIOPinMuxSetup(CONTROL_CONF_GPMC_WAIT0, CONTROL_CONF_MUXMODE(7)); break; case GPIO_31: GPIOPinMuxSetup(CONTROL_CONF_GPMC_WPN, CONTROL_CONF_MUXMODE(7)); break; } }
//****************************************************************************** // PRU Cape Pinmux // This function configures the pinmux for the PRU Cape. //****************************************************************************** void PRUCapePinmux(void) { //****************************************************************************** // LEDS - PRU0 //****************************************************************************** //********************************************* // Blue LED = PR1_PRU0_GPO0 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_ACLKX ) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Green LED = PR1_PRU0_GPO1 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_FSX ) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Orange LED = PR1_PRU0_GPO2 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AXR0 ) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Red LED = PR1_PRU0_GPO3 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKR) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //****************************************************************************** // LEDS - PRU1 //****************************************************************************** //********************************************* // Blue LED = PR1_PRU1_GPO3 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(3)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Green LED = PR1_PRU1_GPO4 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(4)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Red LED = PR1_PRU1_GPO5 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(5)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //****************************************************************************** // Switches //****************************************************************************** //********************************************* // Switch1 = PR1_PRU0_GPI5 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_FSR) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(6); //********************************************* // Switch2 = PR1_PRU0_GPI7 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKX) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(6); //****************************************************************************** // Audio //****************************************************************************** //********************************************* // Audio DIN = PR1_PRU1_GPO0 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(0)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Audio SCLK = PR1_PRU1_GPO1 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(1)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // Audio SYNCn = PR1_PRU1_GPO2 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(2)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //****************************************************************************** // PRU HW UART //****************************************************************************** //********************************************* // UART TXD = PR1_UART0_TXD //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // UART RXD = PR1_UART0_RXD //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(1)) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(5); //********************************************* // UART RTS = PR1_UART0_RTS //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(4); //********************************************* // UART CTS = PR1_UART0_CTS //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(4); //****************************************************************************** // LCD //****************************************************************************** //********************************************* // LCD_RS = PR1_PRU_EDIO_DATA_OUT6 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(6)) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(4); //********************************************* // LCD_E = PR1_PRU_EDIO_DATA_OUT4 //********************************************* *((unsigned int*) SOC_CONTROL_REGS + CONTROL_CONF_LCD_PCLK) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(4); //********************************************* // LCD_DATA4 = PR1_PRU_EDIO_DATA_OUT0 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(6); //********************************************* // LCD_DATA5 = PR1_PRU_EDIO_DATA_OUT1 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS0) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(6); //********************************************* // LCD_DATA6 = PR1_PRU_EDIO_DATA_OUT2 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_VSYNC) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(4); //********************************************* // LCD_DATA7 = PR1_PRU_EDIO_DATA_OUT3 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_HSYNC) = AM335X_PIN_OUTPUT | CONTROL_CONF_MUXMODE(4); //****************************************************************************** // TEMP SENSOR //****************************************************************************** //********************************************* // TEMP1 HDQ/1W output = PR1_PRU_EDIO_DATA_OUT5 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_AC_BIAS_EN) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(4); //********************************************* // TEMP1 HDQ/1W input = PR1_PRU0_GPI14 //********************************************* HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14)) = AM335X_PIN_INPUT | CONTROL_CONF_MUXMODE(6); }