extern "C" void TIM8_CC_IRQHandler()
{
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#if defined(DSM2)
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE ;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
void adcInit()
{
configure_pins(ADC_GPIO_PIN_BAT, PIN_ANALOG | PIN_PORTA);
configure_pins(ADC_GPIO_PIN_VIN, PIN_ANALOG | PIN_PORTA);
configure_pins(ADC_GPIO_PIN_STICK_RV, PIN_ANALOG | PIN_PORTA);
configure_pins(ADC_GPIO_PIN_STICK_RH, PIN_ANALOG | PIN_PORTA);
configure_pins(ADC_GPIO_PIN_STICK_LH, PIN_ANALOG | PIN_PORTA);
configure_pins(ADC_GPIO_PIN_STICK_LV, PIN_ANALOG | PIN_PORTC);
configure_pins(ADC_GPIO_PIN_POTENMETER_1, PIN_ANALOG | PIN_PORTC);
configure_pins(ADC_GPIO_PIN_POTENMETER_2, PIN_ANALOG | PIN_PORTA);
ADC1->CR1 = ADC_CR1_SCAN;//scan mode
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS;//enable adc && enable dma
ADC1->SQR1 = (NUMBER_ANALOG_ADC1-1) << 20 ; // bits 23:20 = number of conversions
ADC1->SQR3 = (ADC_CHANNEL_STICK_LH<<0) + (ADC_CHANNEL_STICK_LV<<5) + (ADC_CHANNEL_STICK_RV<<10) + (ADC_CHANNEL_STICK_RH<<15) + (ADC_CHANNEL_POTENMETER_1<<20) + (ADC_CHANNEL_POTENMETER_2<<25); // conversions 1 to 6
ADC1->SQR2 = (ADC_CHANNEL_BAT<<0) + (ADC_CHANNEL_VIN<<5); // conversions 7 and more
//ADC1->SQR3 = (ADC_CHANNEL_STICK_LH<<0) + (ADC_CHANNEL_STICK_LV<<5) + (ADC_CHANNEL_STICK_RV<<10) + (ADC_CHANNEL_STICK_RH<<15) + (ADC_CHANNEL_POT1<<20) + (ADC_CHANNEL_POT2<<25); // conversions 1 to 6
//ADC1->SMPR1 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12) + (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21) + (SAMPTIME<<24);
ADC1->SMPR2 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12) + (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21);
ADC->CCR = 0 ; //ADC_CCR_ADCPRE_0 ; // Clock div 2
DMA2_Stream0->CR = DMA_SxCR_PL | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC;
DMA2_Stream0->PAR = CONVERT_PTR_UINT(&ADC1->DR);
DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
DMA2_Stream0->NDTR = NUMBER_ANALOG_ADC1;
DMA2_Stream0->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
}
extern "C" void TIM8_CC_IRQHandler()
{
TIM8->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#if defined(DSM2)
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = dsm2Stream[0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
TIM8->DIER |= TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
static void init_pa10_pxx()
{
INTERNAL_RF_ON();
// Timer1, channel 3
setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
// RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE);
GPIO_PinAFConfig(GPIO_INTPPM, GPIO_PinSource_INTPPM, GPIO_AF_TIM1);
GPIO_InitStructure.GPIO_Pin = PIN_INTPPM_OUT;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIO_INTPPM, &GPIO_InitStructure);
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
TIM1->CR1 &= ~TIM_CR1_CEN ;
TIM1->ARR = 18000 ; // 9mS
TIM1->CCR2 = 15000 ; // Update time
TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
TIM1->CCER = TIM_CCER_CC3E ;
TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high
TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
TIM1->EGR = 1 ; // Restart
// TIM1->SR &= ~TIM_SR_UIF ; // Clear flag
// TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM1->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match
TIM1->DCR = 15 ; // DMA to CC1
// TIM1->CR1 = TIM_CR1_OPM ; // Just run once
// Enable the DMA channel here, DMA2 stream 6, channel 6
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream6->PAR = CONVERT_PTR_UINT(&TIM1->DMAR);
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
TIM1->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(TIM1_CC_IRQn);
NVIC_SetPriority(TIM1_CC_IRQn, 7);
}
void extmodulePxxStart()
{
EXTERNAL_MODULE_ON();
// Timer8
setupPulsesPXX(EXTERNAL_MODULE);
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_PinAFConfig(EXTMODULE_GPIO, EXTMODULE_GPIO_PinSource, EXTMODULE_GPIO_AF);
GPIO_InitStructure.GPIO_Pin = EXTMODULE_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(EXTMODULE_GPIO, &GPIO_InitStructure);
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->ARR = 18000 ; // 9mS
EXTMODULE_TIMER->CCR2 = 15000 ; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE ;
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
EXTMODULE_TIMER->EGR = 1 ; // Restart
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
}
extern "C" void TIM1_CC_IRQHandler()
{
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
DMA2_Stream6->CR &= ~DMA_SxCR_EN; // disable DMA, it will have the whole of the execution time of setupPulses() to actually stop
setupPulses(INTERNAL_MODULE);
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6;
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream6->CR |= DMA_SxCR_EN; // enable DMA
INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // enable this interrupt
}
#if defined(TARANIS_INTERNAL_PPM)
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
INTMODULE_TIMER->DIER |= TIM_DIER_UDE;
INTMODULE_TIMER->SR &= ~TIM_SR_UIF;
INTMODULE_TIMER->DIER |= TIM_DIER_UIE;
}
#endif
else {
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
}
}
extern "C" void TIM1_CC_IRQHandler()
{
TIM1->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(INTERNAL_MODULE) ;
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE];
TIM1->DIER |= TIM_DIER_UDE ;
TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
void adcRead()
{
uint32_t i ;
DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
ADC1->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR ) ;
DMA2->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 |DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0 ; // Write ones to clear bits
DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
DMA2_Stream0->NDTR = NUMBER_ANALOG ;
DMA2_Stream0->CR |= DMA_SxCR_EN ; // Enable DMA
ADC1->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
for (i=0; i<10000; i++) {
if (DMA2->LISR & DMA_LISR_TCIF0) {
break ;
}
}
DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
#if !defined(REV3)
// adc direction correct
for (i=0; i<NUMBER_ANALOG; i++) {
if (ana_direction[i] == -1)
Analog_values[i] = 4096-Analog_values[i];
else if (ana_direction[i] == 0)
Analog_values[i] = 0;
}
#endif
}
// Configure DAC0 (or DAC1 for REVA)
// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function
// So maybe it is automatically done
void dacInit()
{
dacTimerInit();
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
configure_pins( 0x0010, PIN_ANALOG | PIN_PORTA ) ;
RCC->APB1ENR |= RCC_APB1ENR_DACEN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN ; // Enable DMA1 clock
// Chan 7, 16-bit wide, Medium priority, memory increments
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
DMA1_Stream5->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 |
DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_CIRC ;
DMA1_Stream5->PAR = CONVERT_PTR_UINT(&DAC->DHR12R1);
// DMA1_Stream5->M0AR = CONVERT_PTR_UINT(Sine_values);
DMA1_Stream5->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA1_Stream5->NDTR = 100 ;
DAC->DHR12R1 = 2010 ;
DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag
DAC->CR = DAC_CR_TEN1 | DAC_CR_EN1 ; // Enable DAC
NVIC_SetPriority(DMA1_Stream5_IRQn, 2) ; // High priority interrupt
NVIC_EnableIRQ(TIM6_DAC_IRQn) ; // TODO needed?
NVIC_SetPriority(TIM6_DAC_IRQn, 7);
NVIC_EnableIRQ(DMA1_Stream5_IRQn) ;
NVIC_SetPriority(DMA1_Stream5_IRQn, 7);
}
static void intmodulePxxStart()
{
INTERNAL_MODULE_ON();
// Timer1, channel 3
setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_PinAFConfig(INTMODULE_GPIO, INTMODULE_GPIO_PinSource, INTMODULE_GPIO_AF);
GPIO_InitStructure.GPIO_Pin = INTMODULE_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(INTMODULE_GPIO, &GPIO_InitStructure);
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
INTMODULE_TIMER->ARR = 18000 ; // 9mS
INTMODULE_TIMER->CCR2 = 15000 ; // Update time
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
INTMODULE_TIMER->CR2 = TIM_CR2_OIS3 ; // O/P idle high
INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
INTMODULE_TIMER->EGR = 1 ; // Restart
INTMODULE_TIMER->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match
INTMODULE_TIMER->DCR = 15 ; // DMA to CC1
// Enable the DMA channel here, DMA2 stream 6, channel 6
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream6->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->DMAR);
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(TIM1_CC_IRQn);
NVIC_SetPriority(TIM1_CC_IRQn, 7);
}
void adcInit()
{
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1Periph_GPIOADC ; // Enable ports A&C clocks
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
#if defined(REV3)
configure_pins(PIN_STK_J1 | PIN_STK_J2 | PIN_STK_J3 | PIN_STK_J4 |
PIN_FLP_J1 | PIN_FLP_J2, PIN_ANALOG | PIN_PORTA) ;
#else
configure_pins(PIN_STK_J1 | PIN_STK_J2 | PIN_STK_J3 | PIN_STK_J4 |
PIN_FLP_J1, PIN_ANALOG | PIN_PORTA) ;
#endif
#if !defined(REV3)
configure_pins(PIN_FLP_J2, PIN_ANALOG|PIN_PORTB);
#endif
configure_pins(PIN_SLD_J1 | PIN_SLD_J2 | PIN_MVOLT, PIN_ANALOG | PIN_PORTC) ;
ADC1->CR1 = ADC_CR1_SCAN ;
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS ;
ADC1->SQR1 = (NUMBER_ANALOG-1) << 20 ; // NUMBER_ANALOG Channels
ADC1->SQR2 = (SLIDE_L<<5) + (SLIDE_R<<10) + (BATTERY<<15) ;
ADC1->SQR3 = STICK_LH + (STICK_LV<<5) + (STICK_RV<<10) + (STICK_RH<<15) + (POT_L<<20) + (POT_R<<25) ;
ADC1->SMPR1 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12)
+ (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21) + (SAMPTIME<<24) ;
ADC1->SMPR2 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12)
+ (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21) + (SAMPTIME<<24) + (SAMPTIME<<27) ;
ADC->CCR = 0 ; //ADC_CCR_ADCPRE_0 ; // Clock div 2
DMA2_Stream0->CR = DMA_SxCR_PL | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC ;
DMA2_Stream0->PAR = CONVERT_PTR_UINT(&ADC1->DR);
DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
DMA2_Stream0->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
}
bool dacQueue(AudioBuffer *buffer)
{
if (dacIdle) {
dacIdle = 0;
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA channel
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(buffer->data);
DMA1_Stream5->NDTR = buffer->size;
DMA1_Stream5->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE ; // Enable DMA channel and interrupt
DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag
DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1 ; // Enable DAC
return true;
}
else {
return false;
}
}
extern "C" void DMA1_Stream5_IRQHandler()
{
DMA1_Stream5->CR &= ~DMA_SxCR_TCIE ; // Stop interrupt
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear flags
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA channel
AudioBuffer *nextBuffer = audioQueue.getNextFilledBuffer();
if (nextBuffer) {
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(nextBuffer->data);
DMA1_Stream5->NDTR = nextBuffer->size;
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
DMA1_Stream5->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE ; // Enable DMA channel
DAC->SR = DAC_SR_DMAUDR1; // Write 1 to clear flag
}
else {
dacIdle = 1;
}
}
extern "C" void PWM_IRQHandler(void)
{
register Pwm *pwmptr;
register Ssc *sscptr;
uint32_t period;
uint32_t reason;
pwmptr = PWM;
reason = pwmptr->PWM_ISR1 ;
if (reason & PWM_ISR1_CHID3) {
// Use the current protocol, don't switch until set_up_pulses
switch (s_current_protocol[EXTERNAL_MODULE]) {
case PROTO_PXX:
// Alternate periods of 6.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 2500 * 2) {
period = 6500 * 2;
}
else {
period = 2500 * 2;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 2500 * 2) {
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses);
sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
case PROTO_DSM2_LP45:
case PROTO_DSM2_DSM2:
case PROTO_DSM2_DSMX:
// Alternate periods of 19.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 2500 * 2) {
period = 19500 * 2;
}
else {
period = 2500 * 2;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 2500 * 2) {
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses);
sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
default:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index++]; // Period in half uS
if (modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index] == 0) {
modulePulsesData[EXTERNAL_MODULE].ppm.index = 0;
setupPulses(EXTERNAL_MODULE);
}
break;
}
}
#if !defined(REVA)
if (reason & PWM_ISR1_CHID1) {
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index++] ; // Period in half uS
if (modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index] == 0) {
modulePulsesData[EXTRA_MODULE].ppm.index = 0;
setupPulsesPPM(EXTRA_MODULE);
}
}
#endif
}
static void init_pa7_dsm2()
{
EXTERNAL_RF_ON();
// Timer8
setupPulsesDSM2(EXTERNAL_MODULE);
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
#if defined(REV3)
configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
#else
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE);
GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8);
GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure);
#endif
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = 44000 ; // 22mS
TIM8->CCR2 = 40000 ; // Update time
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
#else
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
#endif
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM8->CCR1 = dsm2Stream[0] ;
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
TIM8->EGR = 1 ; // Restart
// TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
// TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
TIM8->DCR = 13 ; // DMA to CC1
// TIM8->CR1 = TIM_CR1_OPM ; // Just run once
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
TIM8->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
NVIC_SetPriority(TIM8_CC_IRQn, 7);
}
extern "C" void PWM_IRQHandler(void)
{
register Pwm *pwmptr;
register Ssc *sscptr;
uint32_t period;
uint32_t reason;
pwmptr = PWM;
reason = pwmptr->PWM_ISR1 ;
if (reason & PWM_ISR1_CHID3) {
// Use the current protocol, don't switch until set_up_pulses
switch (s_current_protocol[EXTERNAL_MODULE]) {
case PROTO_PXX:
// Alternate periods of 15.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 5000) { // 2.5 mS
period = 15500 * 2;
}
else {
period = 5000;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 5000) { // 2.5 mS
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(pxxStream[EXTERNAL_MODULE]);
sscptr->SSC_TCR = (uint8_t *)pxxStreamPtr[EXTERNAL_MODULE] - (uint8_t *)pxxStream[EXTERNAL_MODULE];
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
case PROTO_DSM2_LP45:
case PROTO_DSM2_DSM2:
case PROTO_DSM2_DSMX:
// Alternate periods of 19.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 5000) { // 2.5 mS
period = 19500 * 2;
}
else {
period = 5000;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 5000) { // 2.5 mS
setupPulses(0);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(dsm2Stream);
sscptr->SSC_TCR = (uint8_t *)dsm2StreamPtr - (uint8_t *)dsm2Stream;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
default:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]++]; // Period in half uS
if (ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]] == 0) {
ppmStreamIndex[EXTERNAL_MODULE] = 0;
setupPulses(EXTERNAL_MODULE);
}
break;
}
}
if (reason & PWM_ISR1_CHID1) {
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]++] ; // Period in half uS
if (ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]] == 0) {
ppmStreamIndex[EXTRA_MODULE] = 0;
setupPulsesPPM(EXTRA_MODULE);
}
}
}
