void maskAllInt(void) {
int i;
/* for all interrupts (0-115) reset bit 0:3 and 8:11 to disable IRQ and FIQ */
for (i=0; i < MV_IRQ_NR; i++)
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(i), MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(i)) & ~(0xF0F));
}
/*******************************************************************************
* mvSysTwsiInterruptEnable
*
* DESCRIPTION:
* Mask or unmask TWSI main interrupt cause bit.
*
* INPUT:
* chanNum - TWSI channel number.
* mask - MV_TRUE to enable the interrupt,
* MV_FALSE to disable the interrupt.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*
*******************************************************************************/
MV_STATUS mvSysTwsiInterruptEnable(MV_U32 chanNum, MV_BOOL enable)
{
MV_U32 val;
val = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(CPU_MAIN_INT_CAUSE_TWSI(chanNum)));
if (enable == MV_TRUE)
val |= (1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS);
else
val &= ~(1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS);
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(CPU_MAIN_INT_CAUSE_TWSI(chanNum)), val);
return MV_OK;
}
/*
* Enter the requested PM state
*/
static int armadaxp_pm_enter(suspend_state_t state)
{
MV_U32 reg;
switch (state) {
case PM_SUSPEND_STANDBY:
/* Reenable the Uart IRQ in order to wake from it */
/* Enable Uart IRQ */
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_UART0));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_UART0), reg);
/* Disable IPI IRQs */
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_IN_DRBL_LOW));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_IN_DRBL_LOW), reg);
#ifdef CONFIG_MV_ETH_PNC_WOL
printk(KERN_INFO "Entering Wol Mode (Neta IRQs 8,10,12,14 are enabled now)...\n");
/* Reenable the NETA IRQ in order to wake from it */
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE0_FIC));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE0_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE1_FIC));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE1_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE2_FIC));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE2_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE3_FIC));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE3_FIC), reg);
#endif /* CONFIG_MV_ETH_PNC_WOL */
armadaxp_deepidle(SNOOZE);
/* Enable IPI IRQs - return to original state */
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_IN_DRBL_LOW));
reg |= 0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_IN_DRBL_LOW), reg);
/* Disable it since it will be re-enabled by the stack */
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_UART0));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_UART0), reg);
#ifdef CONFIG_MV_ETH_PNC_WOL
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE0_FIC));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE0_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE1_FIC));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE1_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE2_FIC));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE2_FIC), reg);
reg = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE3_FIC));
reg &= ~0x1;
MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(IRQ_AURORA_GBE3_FIC), reg);
printk(KERN_INFO "Exiting Wol Mode (Neta IRQs 8,10,12,14 are disabled now)...\n");
#endif /* CONFIG_MV_ETH_PNC_WOL */
break;
default:
return -EINVAL;
}
return 0;
}