void sgrf_init(void)
{
/* setting all configurable ip into no-secure */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS);
/* secure dma to no sesure */
mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS);
mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS);
dsb();
/* rst dma1 */
mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1),
RST_DMA1_MSK | (RST_DMA1_MSK << 16));
/* rst dma2 */
mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4),
RST_DMA2_MSK | (RST_DMA2_MSK << 16));
dsb();
/* release dma1 rst*/
mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16));
/* release dma2 rst*/
mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16));
}
void rk_module_deinit(void)
{
#ifdef CONFIG_RK_I2C
#if defined(CONFIG_RKCHIP_RK3288)
// soft reset i2c0 - i2c5
writel(0x3f<<10 | 0x3f<<(10+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
mdelay(1);
writel(0x00<<10 | 0x3f<<(10+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
#elif defined(CONFIG_RKCHIP_RK3036) || defined(CONFIG_RKCHIP_RK3126) || defined(CONFIG_RKCHIP_RK3128)
// soft reset i2c0 - i2c3
writel(0x7<<11 | 0x7<<(11+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
mdelay(1);
writel(0x00<<11 | 0x7<<(11+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
#else
#error "PLS config platform for i2c reset!"
#endif
#endif /* CONFIG_RK_I2C */
/* rk pl330 dmac deinit */
#ifdef CONFIG_RK_DMAC
#ifdef CONFIG_RK_DMAC_0
rk_pl330_dmac_deinit(0);
#endif
#ifdef CONFIG_RK_DMAC_1
rk_pl330_dmac_deinit(1);
#endif
#endif /* CONFIG_RK_DMAC*/
/* emmc disable tunning */
rkclk_disable_mmc_tuning(2);
}
void rk_module_deinit(void)
{
#ifdef CONFIG_RK_I2C
#if (CONFIG_RKCHIPTYPE == CONFIG_RK3288)
// soft reset i2c0 - i2c5
writel(0x3f<<10 | 0x3f<<(10+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
mdelay(1);
writel(0x00<<10 | 0x3f<<(10+16), RKIO_CRU_PHYS + CRU_SOFTRSTS_CON(2));
#else
#error "PLS config platform for i2c reset!"
#endif
#endif /* CONFIG_RK_I2C */
}
void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
{
struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr;
struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl;
p_ddr_reg->tag = 0x56313031;
p_ddr_reg->pctladdr = DDR_PCTL_BASE;
p_ddr_reg->phyaddr = DDR_PHY_BASE;
p_ddr_reg->nocaddr = SERVICE_BUS_BASE;
/* PCTLR */
ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U,
(uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35);
pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE;
pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG);
pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_CMDTSTATEN);
pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1);
pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG);
pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG);
pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_TOGCNT1U * 2);
pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLDELAY);
pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG);
pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFIODTCFG1);
pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFIODTRANKMAP);
pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRDATA);
pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRLAT);
pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRDATALAT);
pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITRDDATAEN);
pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYRDLAT);
pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE0);
pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE1);
pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE2);
pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE3);
pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDMIN);
pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDMAX);
pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDDLY);
pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG);
pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITREFMSKI);
pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDI);
pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0);
pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1);
pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITDRAMCLKEN);
pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITDRAMCLKDIS);
pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2);
pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0);
/* PHY */
p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0);
p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1);
p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB);
p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC);
p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11);
p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13);
p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14);
p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16);
p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20);
p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21);
p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26);
p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27);
p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28);
p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30);
p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31);
p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36);
p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37);
p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38);
p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40);
p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41);
p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46);
p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47);
p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48);
p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50);
p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51);
p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56);
p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57);
p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58);
p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGDLL);
p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED);
p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE);
p_ddr_reg->phy.PHY_REGEF = 0;
if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) {
p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG2C);
p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG3C);
p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG4C);
p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG5C);
} else {
p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFB);
p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFC);
p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFD);
p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFE);
}
/* NOC */
p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF);
p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE +
MSCH_DDRTIMING);
p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE);
p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE +
MSCH_READLATENCY);
p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE +
MSCH_ACTIVATE);
p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE +
MSCH_DEVTODEV);
p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1;
p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0;
p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK;
p_ddr_reg->phyplllockval = 0;
/* PLLPD */
p_ddr_reg->pllpdstat = pllpdstat;
/* DPLL */
p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
/* slow mode and power on */
p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN;
p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE;
p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL;
p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET;
p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0);
if (p_ddr_reg->pllselect == 0) {
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 0))
& 0xffff) |
(0xFFFF << 16);
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 1))
& 0xffff);
p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 2))
& 0xffff);
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 3))
& 0xffff) |
(0xFFFF << 16);
} else {
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
}
p_ddr_reg->pllselect = 0;
p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1);
p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK;
p_ddr_reg->dplllockval = DPLL_STATUS_LOCK;
/* SET_DDR_PLL_SRC */
p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13);
p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13))
& DDR_PLL_SRC_MASK)
| (DDR_PLL_SRC_MASK << 16);
p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM;
p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE;
p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0;
p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) &
DDR_PLL_SRC_MASK) |
(DDR_PLL_SRC_MASK << 16);
/* pctl phy soft reset */
p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10);
p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) |
DDRCTRL0_SRSTN_REQ(1) |
DDRPHY0_PSRSTN_REQ(1) |
DDRPHY0_SRSTN_REQ(1);
p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) |
DDRCTRL0_SRSTN_REQ(1) |
DDRPHY0_PSRSTN_REQ(0) |
DDRPHY0_SRSTN_REQ(0);
p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) |
DDRCTRL0_SRSTN_REQ(0) |
DDRPHY0_PSRSTN_REQ(0) |
DDRPHY0_SRSTN_REQ(0);
p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0;
p_ddr_reg->endtag = 0xFFFFFFFF;
}
