static void
i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
BEGIN_BATCH(200, 0);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (1));
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
/* Don't support twosided stencil yet */
OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
ADVANCE_BATCH();
}
static void
i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
BEGIN_BATCH(17);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
ADVANCE_BATCH();
}
/* Push the state into the sarea and/or texture memory.
*/
void
i915_emit_hardware_state(struct i915_context *i915 )
{
/* XXX: there must be an easier way */
const unsigned dwords = ( 14 +
7 +
I915_MAX_DYNAMIC +
8 +
2 + I915_TEX_UNITS*3 +
2 + I915_TEX_UNITS*3 +
2 + I915_MAX_CONSTANT*4 +
#if 0
i915->current.program_len +
#else
i915->fs->program_len +
#endif
6
) * 3/2; /* plus 50% margin */
const unsigned relocs = ( I915_TEX_UNITS +
3
) * 3/2; /* plus 50% margin */
#if 0
debug_printf("i915_emit_hardware_state: %d dwords, %d relocs\n", dwords, relocs);
#endif
if(!BEGIN_BATCH(dwords, relocs)) {
FLUSH_BATCH(NULL);
assert(BEGIN_BATCH(dwords, relocs));
}
/* 14 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_INVARIENT)
{
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) |
CSB_TCB(6, 6) |
CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_TEXKILL_3D_4D |
TEXKILL_4D);
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
/* disable indirect state for now
*/
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);
OUT_BATCH(0);
}
/* 7 dwords, 1 relocs */
if (i915->hardware_dirty & I915_HW_IMMEDIATE)
{
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) |
I1_LOAD_S(1) |
I1_LOAD_S(2) |
I1_LOAD_S(4) |
I1_LOAD_S(5) |
I1_LOAD_S(6) |
(5));
if(i915->vbo)
OUT_RELOC(i915->vbo,
I915_BUFFER_ACCESS_READ,
i915->current.immediate[I915_IMMEDIATE_S0]);
else
/* FIXME: we should not do this */
OUT_BATCH(0);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S1]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S2]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S4]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S5]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S6]);
}
/* I915_MAX_DYNAMIC dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_DYNAMIC)
{
int i;
for (i = 0; i < I915_MAX_DYNAMIC; i++) {
OUT_BATCH(i915->current.dynamic[i]);
}
}
/* 8 dwords, 2 relocs */
if (i915->hardware_dirty & I915_HW_STATIC)
{
struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
if (cbuf_surface) {
unsigned cpitch = cbuf_surface->stride;
unsigned ctile = BUF_3D_USE_FENCE;
if (cbuf_surface->texture &&
((struct i915_texture*)(cbuf_surface->texture))->tiled) {
ctile = BUF_3D_TILED_SURFACE;
}
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK |
BUF_3D_PITCH(cpitch) | /* pitch in bytes */
ctile);
OUT_RELOC(cbuf_surface->buffer,
I915_BUFFER_ACCESS_WRITE,
cbuf_surface->offset);
}
/* What happens if no zbuf??
*/
if (depth_surface) {
unsigned zpitch = depth_surface->stride;
unsigned ztile = BUF_3D_USE_FENCE;
if (depth_surface->texture &&
((struct i915_texture*)(depth_surface->texture))->tiled) {
ztile = BUF_3D_TILED_SURFACE;
}
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_DEPTH |
BUF_3D_PITCH(zpitch) | /* pitch in bytes */
ztile);
OUT_RELOC(depth_surface->buffer,
I915_BUFFER_ACCESS_WRITE,
depth_surface->offset);
}
{
unsigned cformat, zformat = 0;
if (cbuf_surface)
cformat = cbuf_surface->format;
else
cformat = PIPE_FORMAT_A8R8G8B8_UNORM; /* arbitrary */
cformat = translate_format(cformat);
if (depth_surface)
zformat = translate_depth_format( i915->framebuffer.zsbuf->format );
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL |
TEX_DEFAULT_COLOR_OGL |
cformat |
zformat );
}
}
#if 01
/* texture images */
/* 2 + I915_TEX_UNITS*3 dwords, I915_TEX_UNITS relocs */
if (i915->hardware_dirty & (I915_HW_MAP | I915_HW_SAMPLER))
{
const uint nr = i915->current.sampler_enable_nr;
if (nr) {
const uint enabled = i915->current.sampler_enable_flags;
uint unit;
uint count = 0;
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
OUT_BATCH(enabled);
for (unit = 0; unit < I915_TEX_UNITS; unit++) {
if (enabled & (1 << unit)) {
struct pipe_buffer *buf =
i915->texture[unit]->buffer;
uint offset = 0;
assert(buf);
count++;
OUT_RELOC(buf,
I915_BUFFER_ACCESS_READ,
offset);
OUT_BATCH(i915->current.texbuffer[unit][0]); /* MS3 */
OUT_BATCH(i915->current.texbuffer[unit][1]); /* MS4 */
}
}
assert(count == nr);
}
}
#endif
#if 01
/* samplers */
/* 2 + I915_TEX_UNITS*3 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_SAMPLER)
{
if (i915->current.sampler_enable_nr) {
int i;
OUT_BATCH( _3DSTATE_SAMPLER_STATE |
(3 * i915->current.sampler_enable_nr) );
OUT_BATCH( i915->current.sampler_enable_flags );
for (i = 0; i < I915_TEX_UNITS; i++) {
if (i915->current.sampler_enable_flags & (1<<i)) {
OUT_BATCH( i915->current.sampler[i][0] );
OUT_BATCH( i915->current.sampler[i][1] );
OUT_BATCH( i915->current.sampler[i][2] );
}
}
}
}
#endif
/* constants */
/* 2 + I915_MAX_CONSTANT*4 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_PROGRAM)
{
/* Collate the user-defined constants with the fragment shader's
* immediates according to the constant_flags[] array.
*/
const uint nr = i915->fs->num_constants;
if (nr) {
uint i;
OUT_BATCH( _3DSTATE_PIXEL_SHADER_CONSTANTS | (nr * 4) );
OUT_BATCH( (1 << (nr - 1)) | ((1 << (nr - 1)) - 1) );
for (i = 0; i < nr; i++) {
const uint *c;
if (i915->fs->constant_flags[i] == I915_CONSTFLAG_USER) {
/* grab user-defined constant */
c = (uint *) i915->current.constants[PIPE_SHADER_FRAGMENT][i];
}
else {
/* emit program constant */
c = (uint *) i915->fs->constants[i];
}
#if 0 /* debug */
{
float *f = (float *) c;
printf("Const %2d: %f %f %f %f %s\n", i, f[0], f[1], f[2], f[3],
(i915->fs->constant_flags[i] == I915_CONSTFLAG_USER
? "user" : "immediate"));
}
#endif
OUT_BATCH(*c++);
OUT_BATCH(*c++);
OUT_BATCH(*c++);
OUT_BATCH(*c++);
}
}
}
/* Fragment program */
/* i915->current.program_len dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_PROGRAM)
{
uint i;
/* we should always have, at least, a pass-through program */
assert(i915->fs->program_len > 0);
for (i = 0; i < i915->fs->program_len; i++) {
OUT_BATCH(i915->fs->program[i]);
}
}
/* drawing surface size */
/* 6 dwords, 0 relocs */
{
uint w, h;
boolean k = framebuffer_size(&i915->framebuffer, &w, &h);
(void)k;
assert(k);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(((w - 1) & 0xffff) | ((h - 1) << 16));
OUT_BATCH(0);
OUT_BATCH(0);
}
i915->hardware_dirty = 0;
}
BOOL copybox3d( GMABitMap_t *bm_dst, GMABitMap_t *bm_src,
ULONG dst_x,ULONG dst_y,ULONG dst_width, ULONG dst_height,
ULONG src_x,ULONG src_y,ULONG src_width, ULONG src_height )
{
uint32_t dst_format;
uint32_t src_format;
if( !copybox3d_supported() )
{
return FALSE;
}
// buffers in gfx memory ?
if( ! (bm_src->fbgfx && bm_src->fbgfx) )
{
return FALSE;
}
// Max texture size, src and dst must be differend (at least if overlaps)
if( bm_src->pitch/4 > 2048 || bm_src->height > 2048 || bm_dst == bm_src )
{
return FALSE;
}
// src pitch must be long aligmented.
if( bm_src->pitch & 0x3 )
{
bug("[IntelGMA] copybox3d: ERROR bm_src->pitch=%d/n",bm_src->pitch);
return FALSE;
}
if(bm_src->bpp == 4)
{
src_format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
}
else if(bm_src->bpp == 2)
{
src_format = MAPSURF_16BIT | MT_16BIT_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR src_bpp=%d/n",bm_src->bpp);
return FALSE;
}
if(bm_dst->bpp == 4)
{
dst_format = COLOR_BUF_ARGB8888;
}
else if(bm_dst->bpp == 2)
{
dst_format = COLOR_BUF_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR dst_bpp=%d/n",bm_dst->bpp);
return FALSE;
}
D(bug("[IntelGMA:HW] %s()\n", __func__));
LOCK_HW
START_RING(72);
/* invariant state */
OUT_RING( _3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0 );
OUT_RING( _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT) );
OUT_RING( _3DSTATE_DFLT_DIFFUSE_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_SPEC_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_Z_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7) );
OUT_RING( _3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D );
OUT_RING( _3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff) );
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2 );
OUT_RING( 0x00000000 ); /* Disable texture coordinate wrap-shortest */
OUT_RING( (1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY );
OUT_RING( 0x00000000 ); /* Stencil. */
OUT_RING( _3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT );
OUT_RING( _3DSTATE_SCISSOR_RECT_0_CMD );
OUT_RING( 0 );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DEPTH_SUBRECT_DISABLE );
OUT_RING( _3DSTATE_LOAD_INDIRECT | 0 ); /* disable indirect state */
OUT_RING( 0 );
OUT_RING( _3DSTATE_STIPPLE );
OUT_RING( 0x00000000 );
OUT_RING( _3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
/* samler state */
#define TEX_COUNT 1
OUT_RING( _3DSTATE_MAP_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
// Source buffer
OUT_RING( bm_src->framebuffer );
OUT_RING( src_format |
(bm_src->height - 1) << MS3_HEIGHT_SHIFT |
(bm_src->pitch/bm_src->bpp - 1) << MS3_WIDTH_SHIFT );
OUT_RING( (bm_src->pitch/4 -1) << MS4_PITCH_SHIFT );
OUT_RING( _3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
OUT_RING( MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT );
OUT_RING( TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT );
OUT_RING( 0x00000000 );
/* render target state */
// Destination buffer
OUT_RING( _3DSTATE_BUF_INFO_CMD );
OUT_RING( BUF_3D_ID_COLOR_BACK | bm_dst->pitch );
OUT_RING( bm_dst->framebuffer );
OUT_RING( _3DSTATE_DST_BUF_VARS_CMD );
OUT_RING( dst_format |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) );
/* draw rect is unconditional */
OUT_RING( _3DSTATE_DRAW_RECT_CMD );
OUT_RING( 0x00000000 );
OUT_RING( 0x00000000 ); // ymin, xmin
OUT_RING( DRAW_YMAX(dst_y + dst_height - 1) |
DRAW_XMAX(dst_x + dst_width - 1) );
/* yorig, xorig (relate to color buffer?) */
OUT_RING( 0x00000000 );
/* texfmt */
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2 );
OUT_RING( (4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT) );
OUT_RING( ~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) );
OUT_RING( S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT );
/* pixel shader */
OUT_RING( _3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2) );
/* decl FS_T0 */
OUT_RING( D0_DCL |
GET_UREG_TYPE(FS_T0) << D0_TYPE_SHIFT |
GET_UREG_NR(FS_T0) << D0_NR_SHIFT |
((GET_UREG_TYPE(FS_T0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* decl FS_S0 */
OUT_RING( D0_DCL |
(GET_UREG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(GET_UREG_NR(FS_S0) << D0_NR_SHIFT) |
((GET_UREG_TYPE(FS_S0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* texld(FS_OC, FS_S0, FS_T0 */
OUT_RING( T0_TEXLD |
(GET_UREG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(GET_UREG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(GET_UREG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT) );
OUT_RING( (GET_UREG_TYPE(FS_T0) << T1_ADDRESS_GET_UREG_TYPE_SHIFT) |
(GET_UREG_NR(FS_T0) << T1_ADDRESS_GET_UREG_NR_SHIFT) );
OUT_RING( 0 );
// rectangle
// 3--x
// | |
// 2--1
OUT_RING( PRIM3D_RECTLIST | (3*4 - 1) );
OUT_RING( pack_float( dst_x + dst_width) );
OUT_RING( pack_float( dst_y + dst_height) );
OUT_RING( pack_float(src_x + src_width) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y +dst_height) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y + 0 ) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + 0) );
ADVANCE_RING();
DO_FLUSH();
UNLOCK_HW
return TRUE;
}
static void
copy(int fd, uint32_t dst, uint32_t src)
{
uint32_t batch[1024], *b = batch;
struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_execbuffer2 exec;
uint32_t handle;
int ret;
/* invariant state */
*b++ = (_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
*b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT));
*b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_SPEC_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_Z_CMD);
*b++ = (0);
*b++ = (_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
*b++ = (_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
*b++ = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
*b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
*b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY);
*b++ = (0x00000000); /* Stencil. */
*b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
*b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
*b++ = (0);
*b++ = (0);
*b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
*b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
*b++ = (0);
*b++ = (_3DSTATE_STIPPLE);
*b++ = (0x00000000);
*b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
/* samler state */
#define TEX_COUNT 1
*b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
*b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
MS3_TILED_SURFACE |
(HEIGHT - 1) << MS3_HEIGHT_SHIFT |
(WIDTH - 1) << MS3_WIDTH_SHIFT);
*b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
*b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
*b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT);
*b++ = (0x00000000);
/* render target state */
*b++ = (_3DSTATE_BUF_INFO_CMD);
*b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | WIDTH*4);
*b = fill_reloc(r++, b-batch, dst,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
b++;
*b++ = (_3DSTATE_DST_BUF_VARS_CMD);
*b++ = (COLR_BUF_ARGB8888 |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8));
/* draw rect is unconditional */
*b++ = (_3DSTATE_DRAW_RECT_CMD);
*b++ = (0x00000000);
*b++ = (0x00000000); /* ymin, xmin */
*b++ = (DRAW_YMAX(HEIGHT - 1) |
DRAW_XMAX(WIDTH - 1));
/* yorig, xorig (relate to color buffer?) */
*b++ = (0x00000000);
/* texfmt */
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
*b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
*b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
*b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
/* pixel shader */
*b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
/* decl FS_T0 */
*b++ = (D0_DCL |
REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
REG_NR(FS_T0) << D0_NR_SHIFT |
((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* decl FS_S0 */
*b++ = (D0_DCL |
(REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(REG_NR(FS_S0) << D0_NR_SHIFT) |
((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* texld(FS_OC, FS_S0, FS_T0 */
*b++ = (T0_TEXLD |
(REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
*b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
(REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
*b++ = (0);
*b++ = (PRIM3D_RECTLIST | (3*4 - 1));
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = MI_BATCH_BUFFER_END;
if ((b - batch) & 1)
*b++ = 0;
igt_assert(b - batch <= 1024);
handle = gem_create(fd, 4096);
gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
igt_assert(r-reloc == 2);
obj[0].handle = dst;
obj[0].relocation_count = 0;
obj[0].relocs_ptr = 0;
obj[0].alignment = 0;
obj[0].offset = 0;
obj[0].flags = 0;
obj[0].rsvd1 = 0;
obj[0].rsvd2 = 0;
obj[1].handle = src;
obj[1].relocation_count = 0;
obj[1].relocs_ptr = 0;
obj[1].alignment = 0;
obj[1].offset = 0;
obj[1].flags = 0;
obj[1].rsvd1 = 0;
obj[1].rsvd2 = 0;
obj[2].handle = handle;
obj[2].relocation_count = 2;
obj[2].relocs_ptr = (uintptr_t)reloc;
obj[2].alignment = 0;
obj[2].offset = 0;
obj[2].flags = 0;
obj[2].rsvd1 = obj[2].rsvd2 = 0;
exec.buffers_ptr = (uintptr_t)obj;
exec.buffer_count = 3;
exec.batch_start_offset = 0;
exec.batch_len = (b-batch)*sizeof(batch[0]);
exec.DR1 = exec.DR4 = 0;
exec.num_cliprects = 0;
exec.cliprects_ptr = 0;
exec.flags = 0;
i915_execbuffer2_set_context_id(exec, 0);
exec.rsvd2 = 0;
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
while (ret && errno == EBUSY) {
drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
}
igt_assert_eq(ret, 0);
gem_close(fd, handle);
}
else if (i915->flush_dirty & I915_PIPELINE_FLUSH)
OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
}
uint32_t invariant_state[] = {
_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0,
_3DSTATE_DFLT_DIFFUSE_CMD, 0,
_3DSTATE_DFLT_SPEC_CMD, 0,
_3DSTATE_DFLT_Z_CMD, 0,
_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) |
CSB_TCB(6, 6) |
CSB_TCB(7, 7),
_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
void I915EmitInvarientState(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
assert(intel->in_batch_atomic);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
/* Disable independent alpha blend */
OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT));
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
OUT_BATCH(_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */
OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY);
OUT_BATCH(0x00000000); /* Stencil. */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_STIPPLE);
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
}
