static void SerialBSP_AT91_USART3_ClkEn (SERIAL_ERR *perr)
{
CSP_IntDis(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_UART_03);
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_UART_03);
*perr = SERIAL_ERR_NONE;
}
CPU_BOOLEAN CSP_DMA_InitExt (void)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_ch_tbl;
CPU_INT08U ch_nbr;
CSP_IntDis(CSP_INT_CTRL_NBR_MAIN, /* Disable DMA interrupts */
CSP_INT_SRC_NBR_DMA_00);
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_DMA_00); /* Enable DMA controller clock. */
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_reg->IntTCClr = DEF_INT_08_MASK; /* Clear all pending interrupts. */
p_dma_reg->IntErrClr = DEF_INT_08_MASK;
/* Initialize DMA channels register & table */
for (ch_nbr = 0u; ch_nbr < CSP_DMA_CH_MAX_NBR; ch_nbr++) {
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_ch_tbl = &CSP_DMA_ChTbl[ch_nbr];
p_ch_tbl->State = CSP_DMA_CH_STATE_FREE;
p_ch_tbl->CallBackFnctPtr = (CSP_DMA_CALLBACK_PTR )0;
p_ch_tbl->CallBackArgPtr = (void *)0;
p_dma_ch_reg->SrcAddr = 0u;
p_dma_ch_reg->DestAddr = 0u;
p_dma_ch_reg->LLI = 0u;
p_dma_ch_reg->Ctrl = DEF_BIT_NONE;
p_dma_ch_reg->Cfg = DEF_BIT_NONE;
}
p_dma_reg->Cfg = CSP_DMA_REG_CFG_DMA_EN; /* Enable DMA controller. */
(void)CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN, /* Install global DMA interrupt handler. */
(CSP_DEV_NBR )CSP_INT_SRC_NBR_DMA_00,
(CPU_FNCT_PTR )CSP_DMA_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN,
CSP_INT_SRC_NBR_DMA_00);
return (DEF_OK);
}
