/**
* @INTERNAL
* Return the link state of an IPD/PKO port as returned by SRIO link status.
*
* @param ipd_port IPD/PKO port to query
*
* @return Link state
*/
cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
int srio_port = interface - 4;
cvmx_helper_link_info_t result;
cvmx_sriox_status_reg_t srio_status_reg;
cvmx_sriomaintx_port_0_err_stat_t sriomaintx_port_0_err_stat;
cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
result.u64 = 0;
/* Make sure register access is allowed */
srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
if (!srio_status_reg.s.access)
return result;
/* Read the port link status */
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_ERR_STAT(srio_port),
&sriomaintx_port_0_err_stat.u32))
return result;
/* Return if link is down */
if (!sriomaintx_port_0_err_stat.s.pt_ok)
return result;
/* Read the port link width and speed */
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_CTL(srio_port),
&sriomaintx_port_0_ctl.u32))
return result;
if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port),
&sriomaintx_port_0_ctl2.u32))
return result;
/* Link is up */
result.s.full_duplex = 1;
result.s.link_up = 1;
switch (sriomaintx_port_0_ctl2.s.sel_baud)
{
case 1:
result.s.speed = 1250;
break;
case 2:
result.s.speed = 2500;
break;
case 3:
result.s.speed = 3125;
break;
case 4:
result.s.speed = 5000;
break;
case 5:
result.s.speed = 6250;
break;
default:
result.s.speed = 0;
break;
}
switch (sriomaintx_port_0_ctl.s.it_width)
{
case 2: /* Four lanes */
result.s.speed += 40000;
break;
case 3: /* Two lanes */
result.s.speed += 20000;
break;
default: /* One lane */
result.s.speed += 10000;
break;
}
return result;
}
static int cn6xxx_probe(struct rio_dev *dev, const struct rio_device_id *id)
{
u32 data;
cvmx_sriomaintx_m2s_bar2_start_t sriomaintx_m2s_bar2_start;
cvmx_sriomaintx_lcs_ba0_t sriomaintx_lcs_ba0;
cvmx_sriomaintx_lcs_ba1_t sriomaintx_lcs_ba1;
cvmx_sriomaintx_m2s_bar1_start0_t sriomaintx_m2s_bar1_start0;
cvmx_sriomaintx_m2s_bar1_start1_t sriomaintx_m2s_bar1_start1;
cvmx_sriomaintx_m2s_bar0_start0_t sriomaintx_m2s_bar0_start0;
cvmx_sriomaintx_m2s_bar0_start1_t sriomaintx_m2s_bar0_start1;
cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
cvmx_sriomaintx_port_gen_ctl_t sriomaintx_port_gen_ctl;
cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
const char *state;
int index;
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_IR_PI_PHY_STAT(0), &data))
return -1;
switch (data & 0x3ff) {
case 0x0:
state = "Silent";
break;
case 0x2:
state = "Seek";
break;
case 0x4:
state = "Discovery";
break;
case 0x8:
state = "1x Mode Lane 0";
break;
case 0x10:
state = "1x Mode Lane 1";
break;
case 0x20:
state = "1x Mode Lane 2";
break;
case 0x40:
state = "1x Recovery";
break;
case 0x80:
state = "2x Mode";
break;
case 0x100:
state = "2x Recovery";
break;
case 0x200:
state = "4x Mode";
break;
default:
state = "Reserved";
break;
}
dev_info(&dev->dev, "Link state: %s\n", state);
/* Setup BAR2 */
sriomaintx_m2s_bar2_start.u32 = 0;
sriomaintx_m2s_bar2_start.s.addr64 = BAR2_ADDRESS >> 48;
sriomaintx_m2s_bar2_start.s.addr48 = BAR2_ADDRESS >> 41;
sriomaintx_m2s_bar2_start.s.esx = 0;
sriomaintx_m2s_bar2_start.s.cax = 0;
sriomaintx_m2s_bar2_start.s.addr66 = 0; // BAR2_ADDRESS >> 64;
sriomaintx_m2s_bar2_start.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR2_START(0),
sriomaintx_m2s_bar2_start.u32))
return -1;
dev_info(&dev->dev, "BAR2 0x%016llx - 0x%016llx\n", BAR2_ADDRESS,
BAR2_ADDRESS + BAR2_SIZE - 1);
/* Setup Maintinance */
sriomaintx_lcs_ba0.u32 = 0;
sriomaintx_lcs_ba0.s.lcsba = MAINT_ADDRESS >> 35;
sriomaintx_lcs_ba1.u32 = 0;
sriomaintx_lcs_ba1.s.lcsba = (MAINT_ADDRESS >> 24) & 0x7ff;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA0(0),
sriomaintx_lcs_ba0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA1(0),
sriomaintx_lcs_ba1.u32))
return -1;
dev_info(&dev->dev, "Maintenance 0x%016llx - 0x%016llx\n",
MAINT_ADDRESS, MAINT_ADDRESS + MAINT_SIZE - 1);
/* Setup BAR1 */
sriomaintx_m2s_bar1_start0.u32 = 0;
sriomaintx_m2s_bar1_start0.s.addr64 = BAR1_ADDRESS >> 48;
sriomaintx_m2s_bar1_start0.s.addr48 = BAR1_ADDRESS >> 32;
sriomaintx_m2s_bar1_start1.u32 = 0;
sriomaintx_m2s_bar1_start1.s.addr32 = (BAR1_ADDRESS >> 20) & 0xfff;
sriomaintx_m2s_bar1_start1.s.barsize = BAR1_SHIFT;
sriomaintx_m2s_bar1_start1.s.addr66 = 0; // BAR1_ADDRESS >> 64;
sriomaintx_m2s_bar1_start1.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START0(0),
sriomaintx_m2s_bar1_start0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START1(0),
sriomaintx_m2s_bar1_start1.u32))
return -1;
dev_info(&dev->dev, "BAR1 0x%016llx - 0x%016llx\n", BAR1_ADDRESS,
BAR1_ADDRESS + BAR1_SIZE - 1);
/* Setup BAR0 */
sriomaintx_m2s_bar0_start0.u32 = 0;
sriomaintx_m2s_bar0_start0.s.addr64 = BAR0_ADDRESS >> 48;
sriomaintx_m2s_bar0_start0.s.addr48 = BAR0_ADDRESS >> 32;
sriomaintx_m2s_bar0_start1.u32 = 0;
sriomaintx_m2s_bar0_start1.s.addr32 = (BAR0_ADDRESS >> 14) & 0x3ffff;
sriomaintx_m2s_bar0_start1.s.addr66 = 0; // BAR0_ADDRESS >> 64;
sriomaintx_m2s_bar0_start1.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START0(0),
sriomaintx_m2s_bar0_start0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START1(0),
sriomaintx_m2s_bar0_start1.u32))
return -1;
dev_info(&dev->dev, "BAR0 0x%016llx - 0x%016llx\n", BAR0_ADDRESS,
BAR0_ADDRESS + BAR0_SIZE - 1);
/* Set enables */
sriomaintx_core_enables.u32 = 0;
sriomaintx_core_enables.s.imsg1 = 1;
sriomaintx_core_enables.s.imsg0 = 1;
sriomaintx_core_enables.s.doorbell = 1;
sriomaintx_core_enables.s.memory = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_CORE_ENABLES(0),
sriomaintx_core_enables.u32))
return -1;
/* Enable transaction mastering */
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0),
&sriomaintx_port_gen_ctl.u32))
return -1;
sriomaintx_port_gen_ctl.s.menable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0),
sriomaintx_port_gen_ctl.u32))
return -1;
/* Set link I/O enabled */
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0),
&sriomaintx_port_0_ctl.u32))
return -1;
sriomaintx_port_0_ctl.s.o_enable = 1;
sriomaintx_port_0_ctl.s.i_enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0),
sriomaintx_port_0_ctl.u32))
return -1;
if (rio_request_inb_dbell(dev->net->hport, dev, 0, 1,
cn6xxx_doorbell)) {
dev_err(&dev->dev, "Register for incomming doorbells failed\n");
return -1;
}
for (index=0; index<16; index++) {
cvmx_sriomaintx_bar1_idxx_t sriomaintx_bar1_idxx;
sriomaintx_bar1_idxx.u32 = 0;
sriomaintx_bar1_idxx.s.la = index;
sriomaintx_bar1_idxx.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_BAR1_IDXX(index, 0),
sriomaintx_bar1_idxx.u32))
return -1;
}
dev_info(&dev->dev, "SLI_MAC_CREDIT_CNT = 0x%llx\n", c6xxx_read_bar0(dev, CVMX_SLI_MAC_CREDIT_CNT));
if (rio_send_doorbell(dev, 0))
dev_err(&dev->dev, "Sending doorbell failed\n");
if (rio_send_doorbell(dev, 1))
dev_err(&dev->dev, "Sending doorbell failed\n");
return 0;
}
