void
cyg_hal_plf_pci_init(void)
{
cyg_uint8 next_bus;
static int initialized = 0;
if (initialized) return;
initialized = 1;
// Set PCI bases
HAL_WRITE_UINT32(CYGARC_REG_PCI_IO_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_IO));
HAL_WRITE_UINT32(CYGARC_REG_PCI_MEM_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_MEMORY));
// Reset PCI - this does not have the desired effect; devices remain enabled.
HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, CYGARC_REG_SD0001_RESET_PCIRST);
CYGACC_CALL_IF_DELAY_US(100);
// Bring PCI out of reset
HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, 0);
CYGACC_CALL_IF_DELAY_US(10000);
// Set PCI access timeouts/retries to max
HAL_WRITE_UINT32(CYGARC_REG_SD0001_PCI_CTL, (CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT
|CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT));
CYGACC_CALL_IF_DELAY_US(10000);
// Enable controller
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Set memory base
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0x0c000008);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
externC void
_mb93091_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
cyg_pci_init();
// Enable controller - most of the basic configuration
// was set up at boot time in "platform.inc"
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
}
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_ACTIVE)) {
/* It was already active. Turn it off so it gets
configured with a base address which is actually
in the range Redboot can see */
cmd_state &= ~CYG_PCI_CFG_COMMAND_ACTIVE;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0),
CYG_PCI_CFG_COMMAND, cmd_state);
}
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
externC void
hal_ppc405_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state, bridge_state;
if (_init) return;
_init = 1;
// Configure PCI bridge
HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
// Indicate that the bridge has been configured
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
bridge_state |= 0x0001;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
cyg_pci_init();
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
#if defined(CYGPKG_IO_PCI_DEBUG)
diag_printf("Configure PCI bus\n");
#endif
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
if (1) {
cyg_uint8 req;
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);
diag_printf("\n");
diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf(" Vendor Id: 0x%04X", dev_info.vendor);
diag_printf(", Device Id: 0x%04X", dev_info.device);
diag_printf(", Command: 0x%04X", dev_info.command);
diag_printf(", IRQ: %d\n", req);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
#endif
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
if (0){
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
diag_printf("\n");
diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
diag_printf("Device Id : 0x%08X\n", dev_info.device);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
void do_pciedit(int argc, char *argv[])
{
struct option_info opts[5];
unsigned long device;
unsigned long function;
unsigned long offset;
unsigned long value;
unsigned int bus = 0;
bool bus_set;
bool device_set;
bool function_set;
bool offset_set;
bool value_set;
cyg_uint8 devfn;
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
(void **)&bus, (bool *)&bus_set, "bus");
init_opts(&opts[1], 'd', true, OPTION_ARG_TYPE_NUM,
(void **)&device, (bool *)&device_set, "device");
init_opts(&opts[2], 'f', true, OPTION_ARG_TYPE_NUM,
(void **)&function, (bool *)&function_set, "function");
init_opts(&opts[3], 'o', true, OPTION_ARG_TYPE_NUM,
(void **)&offset, (bool *)&offset_set, "offset");
init_opts(&opts[4], 'v', true, OPTION_ARG_TYPE_NUM,
(void **)&value, (bool *)&value_set, "value");
if (!scan_opts(argc, argv, 1, opts, 5, 0, 0, "")) {
return;
}
if (!bus_set) {
diag_printf("Pedit what [bus]?\n");
return;
}
if (!device_set) {
diag_printf("Pedit what [device]?\n");
return;
}
if (device > 32)
{
diag_printf("Invalid Device Number - %d\n", (unsigned int)device);
return;
}
if (!function_set) {
function = 0;
function_set = true;
}
if (function > 7)
{
diag_printf("Invalid Function Number - %d\n", (unsigned int)function);
return;
}
if (!offset_set) {
diag_printf("Pedit what [offset]?\n");
return;
}
if (!value_set) {
diag_printf("Pedit what [value]?\n");
return;
}
#if 0
/* If device number is on the secondary bus, set bus number to 1 */
if (device >= P4205_SERIAL_MEZZ_CFG_ADDR)
bus = 1;
#endif
devfn = CYG_PCI_DEV_MAKE_DEVFN(device, function);
cyg_pcihw_write_config_uint32(bus, devfn, offset, value);
}
void do_pcidump(int argc, char *argv[])
{
struct option_info opts[4];
unsigned long bus;
unsigned long device;
unsigned long function;
unsigned long length;
unsigned int value;
static unsigned int _bus = 0xFFFFFFFF;
static unsigned int _offset = 0xFFFFFFFF;
static unsigned int _function = 0xFFFFFFFF;
static unsigned int _device = 0xFFFFFFFF;
static unsigned int _length = 0xFFFFFFFF;
bool bus_set;
bool device_set;
bool function_set;
bool length_set;
cyg_uint8 devfn;
int i;
int j;
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
(void **)&bus, (bool *)&bus_set, "bus");
init_opts(&opts[1], 'd', true, OPTION_ARG_TYPE_NUM,
(void **)&device, (bool *)&device_set, "device");
init_opts(&opts[2], 'f', true, OPTION_ARG_TYPE_NUM,
(void **)&function, (bool *)&function_set, "function");
init_opts(&opts[3], 'l', true, OPTION_ARG_TYPE_NUM,
(void **)&length, (bool *)&length_set, "length");
if (!scan_opts(argc, argv, 1, opts, 4, 0, 0, "")) {
return;
}
if (!bus_set) {
if (_bus == 0xFFFFFFFF) {
diag_printf("Pdump what [bus]?\n");
return;
}
}
else if (!device_set) {
if (_device == 0xFFFFFFFF) {
diag_printf("Pdump what [device]?\n");
return;
}
}
else
{
_offset = 0;
_device = device;
_bus = bus;
}
if (_device > 32)
{
diag_printf("Invalid Device Number - %d\n", _device);
return;
}
if (!function_set) {
if (_function == 0xFFFFFFFF)
_function = 0;
}
else
_function = function;
if (_function > 7)
{
diag_printf("Invalid Function Number - %d\n", _function);
return;
}
if (!length_set) {
if (_length == 0xFFFFFFFF)
_length = 16;
}
else
_length = length;
#if 0
/* If device number is on the secondary bus, set bus number to 1 */
if (_device >= P4205_SERIAL_MEZZ_CFG_ADDR)
bus = 1;
#endif
devfn = CYG_PCI_DEV_MAKE_DEVFN(_device, _function);
for (i = 0; i < _length; i += 4)
{
diag_printf("%08x: ", _offset);
for (j = 0; j < 4; ++j, _offset+=4)
{
cyg_pcihw_read_config_uint32(_bus, devfn, _offset, &value);
diag_printf("%08x ", value);
}
diag_printf("\n");
}
}
void cyg_hal_plf_pci_init(void)
{
cyg_uint32 bar_ena, start10, start32, end, size;
cyg_uint8 next_bus;
// Program PCI window in CPU address space and CPU->PCI remap
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_LD_OFFSET,
HAL_OCELOT_PCI_MEM0_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_HD_OFFSET,
(HAL_OCELOT_PCI_MEM0_BASE+HAL_OCELOT_PCI_MEM0_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_LD_OFFSET,
HAL_OCELOT_PCI_MEM1_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_HD_OFFSET,
(HAL_OCELOT_PCI_MEM1_BASE+HAL_OCELOT_PCI_MEM1_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_LD_OFFSET,
HAL_OCELOT_PCI_IO_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_HD_OFFSET,
(HAL_OCELOT_PCI_IO_BASE+HAL_OCELOT_PCI_IO_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_IO |
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 6);
// Disable all BARs
bar_ena = 0x1ff;
// Allow PCI bus to access local memory
// Check for active SCS10
start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start10) {
if ((size = __check_bar(start10, end - start10)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
}
}
// Check for active SCS32
start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start32) {
if ((size = __check_bar(start32, end - start32)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
}
}
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0xffffffff);
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, start10);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0xffffffff);
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, start32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
