void HAL_USBInit(uint8_t corenum)
{
/* Enable PLL1 for 48MHz output */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
#if defined(__LPC175X_6X__)
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLL1STS_LOCKED) == 0);
#else
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0);
#endif
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1); /* P0.29 D1+, P0.30 D1- */
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
#if defined(USB_CAN_BE_HOST)
Chip_IOCON_PinMux(LPC_IOCON, 1, 19, IOCON_MODE_INACT, IOCON_FUNC2); /* USB_Power switch */
#endif
#if defined(USB_CAN_BE_DEVICE)
Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1); /* USB_SoftConnect */
#endif
LPC_SYSCTL->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per.*/
#if defined(USB_CAN_BE_DEVICE)
LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */
while ((LPC_USB->USBClkSt & 0x12) != 0x12) ;
HAL_Reset(corenum);
#endif
}
void HAL_USBInit(uint8_t corenum)
{
/* Enable PLL1 for 48MHz output */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0);
#if defined(__LPC175X_6X__)
//LPC_PINCON->PINSEL1 &= ~((3 << 26) | (3 << 28)); /* P0.29 D+, P0.30 D- */
//LPC_PINCON->PINSEL1 |= ((1 << 26) | (1 << 28)); /* PINSEL1 26.27, 28.29 = 01 */
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC1);
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC1);
#if defined(USB_CAN_BE_HOST)
LPC_PINCON->PINSEL3 &= ~(3 << 6);
LPC_PINCON->PINSEL3 |= (2 << 6);
#endif
#elif defined(__LPC177X_8X__) || defined(__LPC407X_8X__)
//LPC_IOCON->P0_29 &= ~0x07; /* P0.29 D1+, P0.30 D1- */
LPC_IOCON->p[0][29] &= ~0x07;
LPC_IOCON->p[0][30] &= ~0x07;
LPC_IOCON->p[0][29] |= 0x1;
LPC_IOCON->p[0][30] |= 0x1;
//Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC1);
//Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC1);
#if defined(USB_CAN_BE_DEVICE)
//LPC_IOCON->P2_9 &= ~0x07; /* USB_SoftConnect */
//LPC_IOCON->P2_9 |= 0x1;
//Chip_IOCON_PinMux(LPC_IOCON, 2, 9, MD_PLN, FUNC1);
LPC_IOCON->p[2][9] &= ~0x07; /* USB_SoftConnect */
LPC_IOCON->p[2][9] |= 0x1;
#endif
#if defined(USB_CAN_BE_HOST)
//LPC_IOCON->P1_19 &= ~0x07; /* USB_Power switch */
LPC_IOCON->p[1][19] &= ~0x07;
LPC_IOCON->p[1][19] |= 0x2;
#endif
#endif
LPC_SYSCTL->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per.*/
#if defined(USB_CAN_BE_DEVICE)
LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */
while ((LPC_USB->USBClkSt & 0x12) != 0x12) ;
HAL_Reset(corenum);
#endif
}
static void Chip_USB_PllSetup(void)
{
/* No need to setup anything if PLL is already setup for the frequency */
if (Chip_Clock_GetClockInputHz(CLKIN_USBPLL) == usbPLLSetup.freq)
return ;
/* Setup default USB PLL state for a 480MHz output and attach */
Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
/* enable USB PLL */
Chip_Clock_EnablePLL(CGU_USB_PLL);
/* Wait for PLL lock */
while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)) {}
}
/* Sets up USB PLL, all needed clocks and enables USB PHY on the chip. USB pins which are
muxed to different pads are not initialized here. This routine assumes that the XTAL
OSC is enabled and running prior to this call. */
void Chip_USB_Init(void)
{
#if defined(CHIP_LPC175X_6X)
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL1 Output = USBCLK = 48MHz = FIN * MSEL, so MSEL = 4.
FCCO = USBCLK = USBCLK * 2 * P. It must be between 156 MHz to 320 MHz.
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1); /* Multiply by 4, Divide by 2 */
/* Use PLL1 output as USB Clock Source */
/* Enable PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
/* Wait for PLL1 to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
/* Connect PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT);
/* Wait for PLL1 to be connected */
while (!Chip_Clock_IsUSBPLLConnected()) {}
#else
/* Select XTAL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = 0x1;
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL output = 48MHz = FIN * MSEL, so MSEL = 4
FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1);
/* Wait for USB PLL to lock */
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0) {}
/* Select PLL1/USBPLL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = (SYSCTL_USBCLKSRC_USBPLL << 8) | 0x01;
#endif /* defined(CHIP_LPC175X_6X) */
/* Enable AHB clock to the USB block and USB RAM. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
}
void HAL_USBInit(uint8_t corenum)
{
/* Just exit if already enabled */
if (!coreEnabled[corenum]) {
/* if other code is not enabled, the enable USB PLL */
if (!coreEnabled[1 - corenum]) {
/* Neither core is enabled, so enable USB PLL first */
Chip_Clock_EnablePLL(CGU_USB_PLL);
/* Wait for PLL lock */
while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED));
}
if (corenum == 0) {
/* For core 0, enable USB0 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
}
else {
/* For core 1, enable USB1 base clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
/* Turn on the phy */
Chip_CREG_EnableUSB0Phy(true);
#if defined(USB_CAN_BE_HOST)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16;
#endif
#if defined(USB_CAN_BE_DEVICE)
/* enable USB1_DP and USB1_DN on chip FS phy */
if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12;
#endif
LPC_USB1->PORTSC1_D |= (1 << 24);
}
coreEnabled[corenum] = true;
}
#if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER))
/* reset the controller */
USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset;
/* wait for reset to complete */
while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ;
/* Program the controller to be the USB device controller */
USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/;
if (corenum == 0) {
/* set OTG transcever in proper state, device is present
on the port(CCS=1), port enable/disable status change(PES=1). */
LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
#if (USB_FORCED_FULLSPEED)
LPC_USB0->PORTSC1_D |= (1 << 24);
#endif
}
HAL_Reset(corenum);
#endif
}
