/* Initialize the SPI */ void Chip_SPI_IF_Init(LPC_SPI_T *pSPI, SPI_MODECONFIG_T *pConfig) { uint32_t EnStat; Chip_SPI_Init(pSPI); EnStat = pSPI->CFG & SPI_CFG_SPI_EN; /* Disable before update CFG register */ if (EnStat) { Chip_SPI_Disable(pSPI); } /* SPI Configurate */ pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) | ((uint32_t) pConfig->SSELPol); if ( pConfig->Mode == SPI_CFG_MASTER_EN ) { /* Rate Divider setting */ pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv); } /* Clear status flag*/ Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD); /* Return the previous state */ if (EnStat) { Chip_SPI_Enable(pSPI); } }
/*Send and Receive SPI Data */ uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) { uint32_t Status; /* Clear status */ Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD); Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF); pXfSetup->TxCnt = pXfSetup->RxCnt = 0; while ((pXfSetup->TxCnt < pXfSetup->Length) || (pXfSetup->RxCnt < pXfSetup->Length)) { Status = Chip_SPI_GetStatus(pSPI); /* In case of TxReady */ if ((Status & SPI_STAT_TXRDY) && (pXfSetup->TxCnt < pXfSetup->Length)) { SPI_Send_Data(pSPI, pXfSetup); } /*In case of Rx ready */ if ((Status & SPI_STAT_RXRDY) && (pXfSetup->RxCnt < pXfSetup->Length)) { SPI_Receive_Data(pSPI, pXfSetup); } } /* Check error */ if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR)) { return 0; } return pXfSetup->TxCnt; }
/* Initialize the SPI */ void Chip_SPI_Init(LPC_SPI_T *pSPI, SPI_CONFIG_T *pConfig) { uint32_t EnStat = pSPI->CFG & SPI_CFG_SPI_EN; Chip_Clock_EnablePeriphClock((pSPI == LPC_SPI1) ? SYSCTL_CLOCK_SPI1 : SYSCTL_CLOCK_SPI0); Chip_SYSCTL_PeriphReset((pSPI == LPC_SPI1) ? RESET_SPI1 : RESET_SPI0); /* Disable before update CFG register */ if (EnStat) { Chip_SPI_Disable(pSPI); } /* SPI Configurate */ pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) | ((uint32_t) pConfig->SSELPol); /* Rate Divider setting */ pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv); /* Clear status flag*/ Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); /* Return the previous state */ if (EnStat) { Chip_SPI_Enable(pSPI); } }
uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) { /* Clear status */ Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD); Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF | SPI_TXCTL_RXIGNORE); pXfSetup->TxCnt = pXfSetup->RxCnt = 0; while (pXfSetup->TxCnt < pXfSetup->Length) { /* Wait for TxReady */ while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {} SPI_Send_Data_RxIgnore(pSPI, pXfSetup); } /* Make sure the last frame sent completely*/ while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_SSD)) {} Chip_SPI_ClearStatus(pSPI, SPI_STAT_SSD); /* Check overrun error */ if (Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXUR) { return 0; } return pXfSetup->TxCnt; }
uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup) { /* Clear status */ Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD); Chip_SPI_SetControlInfo(pSPI, pXfSetup->DataSize, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF); pXfSetup->TxCnt = pXfSetup->RxCnt = 0; while (pXfSetup->RxCnt < pXfSetup->Length) { /* Wait for TxReady */ while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_TXRDY)) {} SPI_Send_Dummy(pSPI, pXfSetup); /* Wait for receive data */ while (!(Chip_SPI_GetStatus(pSPI) & SPI_STAT_RXRDY)) {} SPI_Receive_Data(pSPI, pXfSetup); } /* Check overrun error */ if (Chip_SPI_GetStatus(pSPI) & (SPI_STAT_RXOV | SPI_STAT_TXUR)) { return 0; } return pXfSetup->RxCnt; }